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Stratix
Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.
We found 538 threads matching "stratix"
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Stratix GX
jon - 2009-05-06 11:35:00
I have 54 pcs of a Stratix GX EP2SGX90EF1152C3N I over bought on I
will let them go for $200
I also have 40 pcs of Stratix GX EP2SGX90FF1508C3N
Both products are in original factory packaging. I can also supply on
terms on approved credit.
Thanks,
Jon E. Hansen
(949)864-7745
...
Stratix II GX Transceivers
jjlindula@hotmail.com - 2006-11-29 14:53:00
Hello, I'm looking to do a design involving data rates near 4Gbps and
was looking at using Altera's Stratix II GX transceivers to drive the
data to a 4Gbps single-mode fiber-optic transceiver. I'm interested in
how well the Stratix can perform this task, if anyone has some
experience using the t...CAM, TCAM in Stratix
freechip - 2006-04-21 11:51:00
Hi,
I am working on a 10 Gb Ethernet project (deep packet inspection) and need
to implement CAM in my FPGA. I am using a Stratix GX and I don't think I
can use CAM (internal or external) in the stratix GX Dev Board.
Let me know your thoughts about that.
Thanks a lot.
...Altera-Xilinx interfacing SERDES transcievers problem
vasile - 2007-08-02 14:11:00
Hi,
Who could enlighten me with the followings:
I need to interface a SERDES transciever from a VIRTEX5 FPGA with a
STRATIX II IO. Things would be easiest if I'll have a Stratix II GX
instead of Stratix II, but the GX FPGA has no HARDCOPY II structured
Altera ASIC corespondent, so I can't use...Stratix IV Announced
John Adair - 2008-05-19 14:58:00
Altera have put out a press release announcing Stratix IV. Handbook
http://www.altera.com/literature/hb/stratix-iv/stx4_5v4.pdf.
Interestingly it's gone 40nm and does not appear to have a true 3.3V
compatability so buy your shares in manufacurers of bus switches now.
John Adair
Enterpoint Ltd...Re: equivalent Xilinx FPGA for Altera Stratix II GX-60 ,Altera Stratix II GX-90
Dave Greenfield - 2008-01-31 00:11:00
I suggest also considering transceiver speed, jitter and signal
integrity. Stratix II GX FPGAs provide a production qualified
transceiver speed of 6.375 Gbps which isn't addressed by V5 LXT.
Dave Greenfield
Altera Marketing
...NIOS Board Stratix Edition - FPGA won't configure
vadim - 2004-05-18 19:37:00
I am having problem with my NIOS Stratix Board. I am not
able to download just my own, simple, compiled VHDL code onto
the Stratix FPGA. The device is EP1S10F780C6ES.
After JTAG (ByteBlaster) download finishes, the board resets
and MAX configuration-device loads Stratix with the default
config...What happened to the Cyclone IV?
Philipp Klaus Krause - 2008-11-14 13:24:00
According to Altera's 2005 roadmap it was supposed to be available
shortly after the Stratix IV and far earlier than Stratix IV GX and
Hardcopy IV.
Philipp
...Stratix II
jon - 2009-10-21 10:04:00
Does anyone have any surplus on any of the Stratix II FPGA. Small or
large quantities would help.
Thanks,
Jon E. Hansen
(949)864-7745
...Interfacing FPGA to on-board SRAM Stratix EP1S40F780C5
Edward - 2004-06-11 06:29:00
Hello All,
I am trying to interface the on-board SRAM (IDT71V416 256Kx16) to the
FPGA on the Stratix. It is not installed among the library components
in the SOPC builder so I cannot instantiate it automatically.
I have the datasheet for the SRAM but I need to know where the
address, data p...Re: Now I am really confused!
Paul Leventis (at home) - 2004-08-09 23:18:00
> In the meantime, Altera has jumped on this bandwagon and they multiply
their
> ALE numbers by 1.25.
Jumping to our defense on this one, we clearly state the number of Adaptive
Logic Modules (ALMs) in our Stratix II literature, and a give a separate
"Equivalent Logic Element" count. We us...Stratix GX
jon - 2007-09-26 14:16:00
Can anyone help on finding a home for the Altera Stratix GX chips. I
am in a situation where one of my contracted accounts has purchased
the Altera Stratix GX product prematurely. They are not going to be
doing the build the product was procured for. Basically they are in
a situation where the...altera stratix problem
vlsi_learner - 2005-01-11 01:54:00
I am designing an encryption algorithm using VHDL & targetting it to
Stratix EP1S10F780C6.The problem is that post P&R simulation results
are not correct.however when i target to Stratix EP1S10F780C5, i get
the correct encrypted/decrypted output.How does the speed grade affect
the post P&R outpu...V4 vs. Stratix-II...
Joseph H Allen - 2005-05-12 16:08:00
I'm upgrading a design, and I'm in the early phases of choosing a vendor.
I'm trying to compare parts based on experience I've had in the past, so I'm
focusing on block RAM clock to out delay as a critical performance number:
Altera M4K vs. Xilinx Block RAM clock to out delay, non-registered o...Stratix II GX EP2SGX90FF1508C3N
jon - 2008-06-18 11:44:00
I also have 34 pieces of the Stratix II GX, the part number is
EP2SGX90FF1508C3N
Best Regards,
Jon E. Hansen
(949)864-7745
...Re: Stratix II NIOS sizes ?
Jim Granville - 2004-02-03 19:33:00
Austin Lesea wrote:
> Jim,
>
> *
>
> *.......I have been admonished for commenting on competitors in this
> forum. That will have to be left up to others like yourself.
>
> A careful review of all of the features of St2 will have to be left to
> others.
>
> Perhaps Ray A...Stratix FPGA board up for grabs for cheap.
Alexander - 2010-02-09 21:48:00
Hello!
Sorry to spam, but this is for a very limited audience. I just placed
my crazy expensive Stratix FPGA development board on E-Bay for cheap
if anyone is interested.
Ebay Item: 200437929577
http://cgi.ebay.com/Stratix-FPGA-PCI-X-or-PCI-Development-Board_W0QQitemZ200437929577QQcmdZVie...vertex II vs Stratix
Andy - 2004-04-02 14:09:00
Hi everybody, Could you people help me choose between Altera's Stratix
and Xilinx Vertex II...also as how to analyze the datasheet to
conclude the pros and cons of both the architectures?
thanks
-andy
...EP2S130F1508C3N STRATIX II FPGA
jon - 2008-03-17 13:08:00
Can anyone help me an Altera Stratix EP2S130F1508C3N? I need 500 pcs,
but will take partials.
Thanks in advance for taking the time to look into.
Jon E. Hansen
(949)864-7745
...Stratix DSP Block: Choosing which FFs are enabled
Rajeev - 2004-06-14 20:38:00
I'm trying to increase the speed of my Stratix design and would
like to change which FFs are turned on within a DSP block.
The Stratix handbook shows the DSP path something like this:
[ FF ] [ X ] [ FF ] [ + ] [ FF ]
where [X] is the multiplier block, [+] is an accumulate block
and all r...Downloading some data from flash memory thru JTAG.
2008-04-04 00:22:00
Hi.
I have common configuration scheme for Altera Stratix II: flash memory
+ Max device + Stratix II.
Flash memory configured by FPP method thru JTAG.
Is there any simple method to download flash memory contents thru
Stratix II device and thru JTAG port to computer?
...Stratix II vs Virtex 4
Keith Williams - 2005-03-19 09:43:00
Hello everyone,
I have a rather high performance design that acts as a high through-put data
path with some DSP manipulation on the way through.
I had been rather certain that I was going to move through to production
using Stratix/Stratix II parts. However, the other day I sat down with a
...Timing model for MultiTrack interconnects in Stratix?
Peter Sommerfeld - 2004-01-24 16:41:00
Hi,
I am interested in the timing model of the MultiTrack interconnects on
Stratix.
The timing models for most resources (LEs, M4ks, IOs, etc) are
described in detail in the Stratix handbook, but, curiously, while the
symbols are defined for the MultiTracks (R4, R8, R24, C4, C8, C16) in
th...Help Implementing an 1000Base-T Ethernet on Stratix II GX
jjlindula@hotmail.com - 2007-01-05 19:52:00
Hello, I'm looking to implement an Ethernet Controller to support
1000Base-T on a Stratix II GX and would like to know if anyone could
suggest an IP Core? I've been looking over the Atlera IP web site and
have found some IP's, but I wanted to see what other people were using.
thanks,
joe
...Re: register state when power on
Rob - 2006-07-03 14:30:00
Oddly enough your answer is given in any of Altera's FPGA data sheets.
Below is a sentence pulled from the Stratix data sheet.
User I/O pins are tri-stated during configuration. Stratix and Stratix GX
devices also have a weak pull-up resistors
on I/O pins during configuration that are enab...Choosing the EPC16 or the EPCS64 for Stratix II
jjlindula@hotmail.com - 2007-07-02 17:05:00
Hello, I'm trying to decide to use an EPC16 or EPCS64 to program the
Stratix II EP2S601020C3 on my board. Can any comment which method is
better/faster? Altera's development kits are using the EPCS64 so I
leaning that direction.
Thanks,
joe
...Read from CF - Stratix II
Guy_FPGA - 2009-01-08 14:38:00
Hello there,
I own the NIOS - stratix II development board (
http://www.altera.com/products/devkits/altera/kit-niosii-2S60.html ).
Does anybody know how to read a file from the onboard CF?
I do not want to use an OS on the NIOS processor.
Any reference design is more then welcome . . .
T...stratix fpga pll
ebi - 2005-10-11 12:16:00
hi all dears,
i am new to altera stratix fpgas
i want to know more about plls in the altera FPGA and how can i
produce a clock for my program with plls?
thanks
bye
...Feedback on Stratix III
2008-01-11 08:04:00
Hi everybody,
As Altera claims that Stratix III engineering samples are available
today for some customers who subcribed to the early avaibility
program, I am very interested in the 1st feedback from people who get
already this chip (in term of avaibility, performance, power
consumption...).
...Parallax Stratix Smartpack accessories?
radarman - 2006-11-20 11:38:00
Parallax, the company that makes those nifty little BASIC stamps, is
(or was) selling off the last of the Cyclone and Stratix
"Fast/Smartpack" boards. These are pretty utilitarian boards, with a
custom serial programmer & configuration system, a serial line driver,
a clock oscillator, and a hand...PMC or XMC based on Altera parts (preferably Stratix)
jfh - 2009-12-01 16:10:00
Hi,
On a project requiring intensive processing based on VXS boards we are
looking at ways of increasing the processing power by using a
mezzanine board hosting a large FPGA with fast access memory
resources. The mezzanine would preferably be an XMC type and PMC as a
last resort. We are looki...interface ad9229 with altera stratix II
michael - 2007-03-14 03:28:00
can some one give me a hint on how to interface AD9229 a to d
converter with stratix II lvds interface? the AD9229 output sample
word of 12 bits, however the lvds serdes factor is 10 at the max.
-thanks
...Question: size of Stratix??
Jian Liang - 2004-02-26 22:46:00
I am looking for the die size of Stratix EP1s10 FPGA. It will be highly appreciated if anybody can give me a hint where to find such information. Any number in terms of mm^2, lamda, transistor count or gate count will be fine. I have checked the data sheet but could not find any.
Thanks for car...July 20th Altera Net Seminar: Stratix II Logic Density
Paul Leventis (at home) - 2005-07-19 08:53:00
On Wednesday, July 20th @ 11 AM PST, two of my colleagues (Alex Grbic and
Paul Ekas) will be giving a net seminar comparing Stratix II and Virtex-4
logic densities. They will describe the logic architectures of these two
families, compare logic densities between these two families, discuss ...Stratix to PC communication
2006-10-29 21:36:00
Hi, I am an undergrad student attempting to build a software defined
radio device on a Stratix EP1S80 DSP Development Board, and am hoping
to do most of the signal processing on a PC. I therefore need to
transfer data to the PC at a rate of about 1 MBps (twice the AM IF
frequency of 455 kHz at 8...Altera M9K + M144K RAM: do they get combined
Poojan Wagh - 2009-07-26 01:21:00
Will Quartus automatically allocate RAM to both M9K and M144K blocks?
Is there any performance improvement to having it all be in a single
block type (M144K for example)?
I need to allocate 6 Mbits of RAM in an application. (I'd prefer it to
be self-contained on the FPGA.) I'm comparing Xilinx...Stratix open-drain pins
ernie - 2005-07-05 20:05:00
Hi,
Anyone know if I can configure the output pins of a Stratix FPGA to be
open-drain?
I need open-drain outputs to interface with an SMBus slave device.
Thanks,
Ernie
...Re: Altera LVDS Transceiver Megafunction - ALTLVDS - question
Subroto Datta - 2004-09-01 14:44:00
Hi Vadim,
Detailed information on LVDS usage for Stratix devices can be found
in Volume 2, Chapter 5 of the Stratix Handbook. This is available
online at http://www.altera.com/literature/hb/stx/ch_5_vol_2.pdf
This Chapter has 76 pages and covers all aspects of High Speed
Differential I/O In...Heat Sink for Stratix
Patrick - 2005-07-21 09:56:00
Hi,
Is there anybody who have utilized a heat sink for stratix FPGA
I need a thermal resistance less than 6°C/W because the power
consumption of my design is 3.8W... and without heat sink the maximum
power dissipation is 2,4 W...
Thanks
...Boot problem Stratix Kit EP1S25
Patrick - 2005-06-08 09:27:00
Hello,
I'm working on a project where we utilize 2 EP1S25 Stratix Evaluation
board.
We have directly connected +5V, +3.3V and +1.5V onto the board
and we have problems at boot, sometimes there's a card where the fpga
is not programmed (LED PROG OFF), only LED D8 ON (+3.3V)
do you have ...