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VHDL
Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.
We found 3753 threads matching "vhdl"
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The most relevant threads are listed first
VHDL gate level from Xilinx XST
Laurent Gauch - 2004-09-21 19:10:00
Hi all,
I need to generate a part of my VHDL project as a VHDL gate level IP, in
the goal to protect my generic IP core.
In fact, I want to protect my own PCI core before delivering the complet
VHDL project.
My question:
Is this possible to do a VHDL gate level Netlist from XST.
Then ...
configuration for a mixed mode VHDL-verilog lang
Rakesh YC - 2004-07-09 04:05:00
Hi all
My problem is I'd like to choose a VHDL file instantiated inside
verilog via VHDL
configuration
To summerize: I have a hierarcy: "top:vhdl - verilog - Verlog -vhdl:
bottom" How to write a vhdl configuration to select the file for the
bottom instantiation?
Rakesh YC
...VHDL or verilog
CMOS - 2006-02-16 10:47:00
hi,
ive completed a introductory book on vhdl, but not mature enough to do
a real world complex designs using vhdl. i've been serching for
tutorial guids to learn advanced vhdl, preferebly with case studies,
but found non. most of the books on vhdl are introductory level. Some
advanced vhdl boo...Getting started VHDL, VHDL for Dummies, Easy Steps for FPGA experiments
Kutaj Vamor - 2005-09-25 05:33:00
Dear FPGA and VHDL Experts,
I am new to FPGA and VHDL. I would like to learn VHDL and start
experimenting FPGA. I beleive I learn faster and better by experimenting.
What would you recommend for beginners like me to getting started with VHDL
and FPGA experimentation ?
Which SW (for WinXP an...Combining Schematic and VHDL code in Webpack 8.1 ??
Per Jensen - 2006-07-19 18:09:00
Hello!
I am a beginner in VHDL programming. i am programming an Xilinx XC9572XL
at the moment, and i have so far used VHDL programming.
I am a little bit unsure, if i can combine VHDL and Shcematic, so a part
of the circuit is described by Schematic, and another by VHDL. Is it
possible, ...AWGN in VHDL
MACEI'S - 2003-09-09 11:21:00
Hi guys,
Does anybody have any idea or any link or code for Additive White
Gaussian Noise in VHDL ? Or any body have written it or not ?
Also how to generate Random Number's in VHDL?
Thanks
Rgds
Macie
...VHDL to Verilog Converter
Ambreen Ashfaq Afridi - 2008-06-03 01:40:00
Hi im looking for a vhdl to verilog converter. Im working with Trimode
Ethernet MAC core which is written in VHDL. I have to modify this code
but the problem is that I dont have any knowledge of VHDL. I do
programming in Verilog.Plz send me any link for the converter.
Thank you
Regards,
Ambree...Verilog vs VHDL
Kishore - 2006-05-23 17:46:00
Hi,
I know this has been brought up many times in various groups but
here is my view on them and I would really appreciate some
clarification. I started working on FPGA design and stuff some 3 months
back or so. All the time I was switching back and forth between verilog
and VHDL for var...VHDL Packages, Coding Styles for Arithmetic Operations and VHDL-200x Additions
Amal - 2008-12-03 09:41:00
Here is a presentation I did a while ago summarizing the VHDL
packages, arithmetic , coding styles and the new features of
VHDL-200x.
http://www.slideshare.net/akhailtash/vhdl-arithmetic-presentation/
Enjoy,
-- Amal
...Altera and VHDL library
Clemens Hermann - 2005-04-11 09:38:00
Hi,
with the latest quartus II software I created two VHDL packages. After
testing the packages I wanted to combine them in a custom VHDL library
with no success. My goal is to have a directory that contains the
library (preferrably precompiled) so that I can pass it around and it
could be us...VHDL modelling USB device
ALuPin - 2004-09-06 08:22:00
Hi VHDL folks,
does somebody know if there are VHDL models available for
USB devices ? A simple model (behavioral) would do the
job.
Any hints are appreciated.
Thank you for your help.
Rgds
...VHDL comments in Vim?
Peter Sommerfeld - 2003-12-17 23:16:00
Hi folks,
I'm getting tired of commenting large blocks of VHDL code by hand.
Anyone know of any Vim scripts that can comment/un-comment a VHDL
block?
A cursory Google search brings up either nothing or way too much stuff
to sift through depending on my search terms ("vhdl vim comment").
...Re: Need help regarding xupv2p board....
Newman - 2008-07-18 03:52:00
On Jul 18, 1:49=A0am, Wasif Shams wrote:
> I bought this board so that I can write the whole software using just
> VHDL. but only info i can find is... to use Power PC =A0or microblaze
> core using EDK and then have periphirals using VHDL.
>
> I tried to use JTAG to program the PROM to ...Verilog and VHDL mix
Remis Norvilis - 2004-02-12 21:55:00
I wonder if it is possible to synthesize on one chip VHDL and Verilog IP
cores. I suppose the VHDL to Verilog or vice versa translator could be
used.
Ideas are welcome.
Remis
--
************************************************
To reply, remove > .spam < and > .fake <
...Good VHDL reference?
Nico Coesel - 2007-09-11 15:33:00
It seems I have misplaced my VHDL book a long time ago and I can't
figure out where I left it. In short: I need a new VHDL book :-(
Can anyone recommend a good generic VHDL reference? I'm not looking
for a book with a particular bias towards fpga design, asic design, or
simulation.
--
R...Re: How to write compact DFF chain?
Thomas Stanka - 2006-03-28 01:24:00
Xpost from OP, FUp2 comp.lang.vhdl
Davy schrieb:
> Sometimes I have to write long DFF chain like below:
In VHDL you would write
if reset_active then
DFF '0');
elsif rising_edge(Clk)
DFF ...VHDL or Verilog
Clemens Hagen - 2005-04-21 05:23:00
Hello
I have a very basic question. Normally you have the choice if you want to
use VHDL or Verilog for
describing you hardware architecture. I would be interested when do you
decide for VHDL and when for
Verilog. Are the special cases when it makes more sense to use one or the
other lang...VHDL model for Micron SDRAM simulation ?
sjulhes - 2006-06-26 06:23:00
Hello all,
I'm desigining a Xilinx FPGA with a sdram controller for a MT48LC8M16A2-75
memory but I can not find anymore the VHDL model on the Micron's website !
Does someone know if it still possible to get a VHDL from Micron ?
As there still verilog models on the Micron's website and as ...XML for VHDL documention and structural description of Hardware SoC
Amontec Team - 2003-07-11 10:29:00
Hi VHDL GNU men,
Amontec is interested to build an auto-documentation of our VHDL
libraries, cell-by-cell.
The documentation will stay basic, like :
general description
port description
generic description
implementation description
license description
note description
The goal is t...Xilinx Floating Point C Simulation aka VHDL/Verilog --> C Conversion?
Simon Heinzle - 2006-06-26 10:31:00
Hi Guys,
I need a C Simulation of some Floating Point Cores from the Xilinx coregen.
I thought about automatically converting the behavioral VHDL code to C, e.g.
with V2C or VHDL-2-C (found via comp.lang.vhdl FAQ part 3).
While I'm investigating this -- has anyone in this group already don...Writing VHDL, Software dummy!
2006-09-18 07:31:00
I have a couple of questions regarding VHDL and FPGAs as I am starting
a project on them shortly0. Before I start I would like to apologize
for my lack of knowledge on them. I am a software developer not a
hardware so you might have to take this into consideration when
explaining.
I know V...using shared vhdl code in customer ipif block
Frank van Eijkelenburg - 2007-02-15 16:21:00
Hi,
I have a small microblaze system with my own ipif peripheral. In this peripheral
I want to use a vhdl block which is also used in another part of my project. Is
this possible? Because when building the system, the edk looks in the
pcores/ /hdl/vhdl directory for sources (where it doesn...VHDL vs Verilog
whygee - 2010-02-12 19:15:00
hi,
recently I read a quote about VHDL vs Verilog,
along the lines of "VHDL is made by SW people who
don't understand HW and vice versa"...
Does anybody know the exact wording and origin ?
yg
--
http://ygdes.com / http://yasep.org
...Port mapping a Verilog component in a VHDL design
ALuPin - 2004-01-15 10:50:00
Dear Sir or Madam,
I have the following problem:
I have a simulation component which is written in Verilog (not a trivial one
which could be translated to VHDL).
My toplevel design and all other components are written in VHDL.
My question:
Is it possible to include this Verilog compone...co-sim for handel C with modelsim vs pure modelsim VHDL simulation
2008-04-30 12:25:00
Hi,
has anybody tried using co-sim for Handel C with modelsim? I managed
to set up the co-sim environment, and got the handel C code to work
with my EDK generated microblaze environment (in VHDL). In short, I am
using handel C to build a peripheral which i attached to microblaze
via the FSL b...Code blocks to realize this in VHDL
mstanisz - 2009-05-05 17:27:00
I've searched a little more and found that if I can somehow merge Ben
Cohen's 0 ohm device
(http://groups.google.com/group/comp.lang.vhdl/msg/7d14832588a0cabb) with a
bi-directional MUX
(http://www.tek-tips.com/viewthread.cfm?qid=1188582&page=7), then I might
be able to create the VHDL module I woul...Creating EDIF from Verilog, then using VHDL wrapper
Robin Bruce - 2006-07-20 12:13:00
Hi group, here's a question:
Can I synthesise a component described in Verilog, obtain an EDIF, then
write a VHDL wrapper around it so as to integrate it into a greater
VHDL project.
yours in ignorance,
Robin
...I need a good reference for VHDL
Teece - 2008-10-08 12:49:00
Hi,
I have been writing Verilog code for many years but the time has come for me
to learn VHDL. Please recommend either a book or web reference or learning
VHDL that would be good for someone that is experienced in FPGA architecture
and Verilog.
Thank You
Tom
tom_cip_11551@hotmail.com
...how to use the design results of the vhdl code for a program in C code
lolita grenoble - 2010-03-15 05:51:00
hello,
i need help.
i work over an algo in C langage that verifies a design described in
VHDL
for it, i want take all informations from my vhdl code for use them in
my programme in C and i don't know how.
...how to read bmp file in vhdl
suni - 2010-02-20 09:47:00
helo
i am in B.E.-E&TC,doing project on DIGITAL WATER MARKING TECH.. I
need to convert matlab code in to vhdl for downloading,if not then how
to read bmp file in vhdl?..Can u please help me out..
...ieee_ proposed library
FPGA - 2008-01-14 15:54:00
Hello all,
I am trying to use some of the proposed functions by IEEE which are
still awaiting approval. http://www.vhdl.org/vhdl-200x/vhdl-200x-ft/packages/float_pkg_c.vhdl
I am getting the following errors
**Error: C:/Modeltech_pe_edu_6.3c/examples/util_top.vhd(58): Library
ieee_proposed n...advanced vhdl lerning
CMOS - 2006-02-04 11:00:00
hi,
i've completed a introdutory vhdl book and done several small scale
designs using vhdl for FPGA implementations. However the book i read
does not cover any advanced topics or designs that we meet in real
life, like micro-controllers, USB interfaces, etc. i' ve serched the
net for books and ...16550 VHDL code
2005-10-10 03:36:00
Hello,
I'm currently writing VHDL code for an Altera cyclone, the EP1C6. One
of the modules i need is an 16550 compatible UART which has to
communicate through an ISA bus (PC104).
My question is if somebody has the VHDL code for it, or can tell me
where i can find code (i've already asked q...Building Gradually Expertise on VHDL/Verilog Design
2007-05-30 18:50:00
Hi,
i have been reading the VHDL language over the last week and now i
want to put what i have learned so far into practice but don't know
really from where to start. As such, i am just wondering if there is
any lab book or a web based tutorials that help a newbie like me to
gradually get a g...WebPack - mixed design flow
Valentin Tihomirov - 2003-09-13 09:52:00
My system has netlist in EDIF while some of technology elements used in the
netlist are
described in a separate VHDL file at logic level. WebPack supports only pure
EDIF, schematic, Verilog or VHDL design flows. Is ther a way to compile a
mixed design?
That is, I first elaborate VHDL and then l...Mixed RTL ,XILINX EDK
mack - 2004-11-07 04:56:00
Hi,
I want to add my peripheral(which has both VHDL and Verilog design
files) into xilinx MB system.I am using XILINX 6.3 currently.I went
thru CREATE/IMPORT PERIPHERAL WIZARD.There in no option available
there to mention that my design has both VHDL and Verilog.But I could
succesfully add my...from VHDL to FPGA
elesser - 2006-06-11 15:50:00
Hi everyone,
I'm a student electronics and computer engineering, and I've already
got quite a bit of experience with hardware design in general and with
VHDL.
I was wondering if someone knows a good reference or book that explains
what the VHDL compiler actually does with the code, to conve...Need help with VHDL simulation with SPW in Linux
dang_hut@yahoo.com - 2007-02-19 04:52:00
Hi every one.
I am newbie in FPGAs, although I can write VHDL.
I already setup a copy of Cadence SPW 4.82 from my company to study
FPGA myself.
My OS is Scientific Linux 3.08 (clone of Redhat Enterprise 3.x).
My purpose is to design in SPW by using fixed-pointed HDS, and
generate to VHDL to ...Info request about Synplify and Foundation usage
2008-09-16 12:12:00
Dear all,
I'm try to use VHDL code with some old XC5202PQ100-6 part that I've
from my old design. Old design was did by using Foundation 2.1i and
Schematic Entry, now I'm searching a way to use the VHDL coding to do
some simple example and learn VHDL. My Foundation tools was only a
base install...hex rep. in VHDL
anupam - 2005-10-27 23:40:00
hi,
I have a small query in VHDL language.
Like we write in Verilog
fifo_data ...