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Verilog
Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.
We found 2440 threads matching "verilog"
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Verilog books
Alex Weddell - 2004-09-17 13:48:00
Hi,
Can anyone recommend a good book on verilog? I've got some experience with
VHDL, but am looking for a book on verilog with an emphasis on synthesisable
design. Inclusion of the verilog 2001 additions would also be nice!
Thanks in advance,
Alex
...
verilog task and vhdl
carlob - 2011-06-03 05:54:00
Hi all,
I've a functional model of a PHY chip in verilog with a lot of tasks to
stimualte change on signals at the interface (and not only)...
Unfortunately I'm not experienced with verilog...I would write a testbench
in vhdl and reuse the model in verilog...
How to call a verilog task inside a...Re: Graphic LCD
Marco - 2005-02-19 17:05:00
I read the article and it is very interesting, but the code seems to be written in verilog, or pseudi verilog.
Where I can find a brief verilog manual?
...Verilog, VHDL, sync and async resets
johnp - 2011-08-10 18:53:00
We need to code some modules in both VHDL and Verilog and would like
to use a parameter/generic
to control inferring sync or async resets. Is there a clean way to
code this that is similar in both
VHDL and Verilog?
For example, we could try to use `define in Verilog, but this won't
port wel...Verilog tutorial by John Sanguinetti
Eric Crabill - 2006-01-24 13:41:00
Hi,
I'm looking for a functional URL that hosts the Verilog tutorial by John
Sanguinetti. Neither of these seem to work:
http://turing.une.edu.au/~comp283/cdrom/Content/Tutorials/Verilog/
http://vol.verilog.com/
I have tried contacting what appears to be the primary/official site
(vol...Call VHDL module from Verilog
egadget1 - 2008-05-06 15:38:00
Hi,
I have a basic question. Is is possible in the xilinx ISE enviroment
to make a verilog wrapper of some VHDL code. I don't want to recode
it in verilog.
Thanks
Rob
...Atmel CPLD development tools for verilog
sri - 2005-06-08 00:47:00
Hi,
Currently I have verilog design files ready for a CPLD implementation
and am planning to use a Atmel AT15xx series CPLD.
But I am having difficulty in finding the right Atmel development
software.
As per the Atmel website, Prochip supports Verilog, but when installed
I am not able to c...Verilog and VHDL mix
Remis Norvilis - 2004-02-12 21:55:00
I wonder if it is possible to synthesize on one chip VHDL and Verilog IP
cores. I suppose the VHDL to Verilog or vice versa translator could be
used.
Ideas are welcome.
Remis
--
************************************************
To reply, remove > .spam < and > .fake <
...VHDL or Verilog
Clemens Hagen - 2005-04-21 05:23:00
Hello
I have a very basic question. Normally you have the choice if you want to
use VHDL or Verilog for
describing you hardware architecture. I would be interested when do you
decide for VHDL and when for
Verilog. Are the special cases when it makes more sense to use one or the
other lang...Wow! No TestbenchWow!
rickman - 2011-01-27 09:22:00
This is the first project I've done in Verilog in many years. With a
long history in VHDL I have a new perspective and am seeing Verilog in
a different way. I am finding some of the differences to be pretty
interesting actually.
I've already commented on the lack of the wildcard sensitivity ...Verilog module in VHDL project - ISE 13
Mike Harrison - 2012-01-03 07:49:00
I want to use the Xilinx Spartan-6 XAPP495 HDMI/DVI transmit/receive modules, which are written in
Verilog, in a new VHDL project, as I'm much more familiar with VHDL - I don't do enough FPGA stuff
to justify the time to learn a new language for one project.
Can anyone point me towards how I c...Virtex-4 ML403 16x2 LCD
Shela - 2006-12-05 13:06:00
HI all,
I am a student. I am new to verilog and FPGA.
I have a question.
How do I use the 16x2 LCD which is on the development board?
I have a verilog code which I want the LCD to load the ASCII char from
the verilog code I written. The verilog code is just a few shift
register acting like...verilog parser question about `defines
raphfrk - 2007-07-25 05:10:00
I have a set of verilog files that uses `defines. The same `define is
applied to each file to select which code to use.
Is there a way to setup Xilinx ISE so that when processing all verilog
files it assumes that a certain `define has been defined ?
...Project Navigator / Verilog / +define
johnp - 2007-05-23 13:53:00
I'm having a problem with Xilinx Navigator "discovering" a Verilog
design hierarchy.
I've inherited some IP that requires that a Verilog `define be set to
specify
the modules to include into the design. However, when Navigator starts
up
and builds the design hierarchy, I see no way to tell i...Project Navigator / Verilog / +define
johnp - 2007-05-23 14:48:00
I'm having a problem with Xilinx Navigator "discovering" a Verilog
design hierarchy.
I've inherited some IP that requires that a Verilog `define be set to
specify
the modules to include into the design. However, when Navigator starts
up
and builds the design hierarchy, I see no way to tell i...Using bidirectional pins in Verilog
Giorgos Tzampanakis - 2010-03-03 14:33:00
I'm trying to use bidirectional pins in Quartus with Verilog.
What's the correct way to do it? Altera has some example code:
http://www.altera.com/support/examples/verilog/ver_bidirec.html
But I don't really understand it. For example, it says it can
drive the value b out but I can't see b...Verilog examples???
Amir Intisar - 2005-04-11 20:27:00
Hello, does anyone know a good website that has examples of verilog
programs you can implement on FPGA's. I have implemented basic
programs that use the LED's, switches and push buttons. However, I am
looking for verilog programs that can show me how to utilise the I/O
expansion sockets, VGA co...systemc to verilog translator v0.5
Javier Castillo - 2005-10-10 08:01:00
Hello,
We have released the version 0.5 of the SystemC to Verilog
Synthesizable Subset Translator, wich includes support for structures
translation from SystemC to Verilog.
You can download it from
http://www.opencores.org/projects.cgi/web/sc2v/overview
Javier Castillo
...Verilog vs VHDL
Kishore - 2006-05-23 17:46:00
Hi,
I know this has been brought up many times in various groups but
here is my view on them and I would really appreciate some
clarification. I started working on FPGA design and stuff some 3 months
back or so. All the time I was switching back and forth between verilog
and VHDL for var...How can I see the waveform of my verilog codes?
mikelinyoho - 2005-08-22 16:01:00
Regards:
I use "Icarus Verilog" as a synthesis and simulation tool.But How can I
see the
waveform of my verilog codes?
thank you
may goodness be with you all
...XST Tool - Want a verilog simulation netlist
Varun Jindal - 2004-09-28 12:21:00
Hello,
I want to compare two designs, one of which is written in verilog
while the other one is in vhdl. the testcases are also written in
verilog. while running the vhdl design, (using XST VHDL) .. the design
compiles without error, but i couldnt figure out a way to generate the
simulation n...Re: modelsim
fazulu deen - 2007-08-30 09:00:00
Jon Beniston wrote:
> On 30 Aug, 10:21, fazulu deen wrote:
> > Hai all,
> >
> > Can any one suggest with an example how to run c++ code in modelsim
> > simulator...I didnt understand the example mentioned in modelsim user
> > guide..Anyone tried this??
>
> What didn't you u...VHDL to Verilog Converter
Ambreen Ashfaq Afridi - 2008-06-03 01:40:00
Hi im looking for a vhdl to verilog converter. Im working with Trimode
Ethernet MAC core which is written in VHDL. I have to modify this code
but the problem is that I dont have any knowledge of VHDL. I do
programming in Verilog.Plz send me any link for the converter.
Thank you
Regards,
Ambree...Delays in verilog
Gerr - 2005-08-11 02:36:00
Hi,
I'm a bit confused by the do's and dont's of delay's (#) in verilog,
like the following snippet :
always @(posedge clk)
load_r ...Verilog simple dual port memory with different input and output widths?
davew - 2007-09-18 13:41:00
Has anyone got any example Verilog code for this? I'm currently using
Quartus wizard generated code and wrapping it up in a Verilog module
so I can use my own parameters instead of running the wizard each time
I need a new variation (which is a complete pain). I thought that
perhaps inferring ...Which to learn: Verilog vs. VHDL?
Michael - 2008-04-14 09:18:00
Howdy - I'm just beginning with FPGAs. I am using a Spartan 3E Starter
Kit with Xilinx ISE. I am an electrical engineer by training and did
some verilog in my collegiate days - but that was quite some time ago
and it is all very fuzzy now. I have decided that as an EE I should be
familiar with F...Good, affordable verilog simulator
Paul Taddonio - 2005-03-08 09:21:00
Can anybody recommend a good PC-based verilog simulator for substantially less than $4500?
I am a new hire at a company which spent big bucks on ModelSim just two years ago. Unfortunately we purchased VHDL and I am a verilog designer. We have a tight schedule so I will stick with the familiar lan...Number of Modules in a Verilog File
Jiten - 2006-08-31 02:32:00
Hi,
Is there any method to increase number of verilog modules/instances in
a single verilog file, While sythesizing with Xilinx Project navigator?
If there are more than about 50 modules in a single verilog file it is
not taken by project navigator, and it shows a '?' ahead of these
modules. ...Where to start???
2007-02-16 17:22:00
Hi,
I'm very interested in starting to learn about fpgas. I tried finding
if there was anything about it at local colleges, but it seems a
little to specialised! I'm quite adept at software engineering (C++/
Java etc...), but I haven't done any assembly, or worked very close
with any hardware...Verilog Book for VHDL Users
rickman - 2011-01-14 11:44:00
I am finally going to learn Verilog for real after using VHDL for 15
years. I've done a little work with Verilog and found it relatively
easy to use. Now I want to learn the details and especially how not
to make mistakes.
VHDL has the problem of not letting you do things unless you make it
...Verilog vs VHDL for Loops
Andre Bonin - 2004-09-18 01:30:00
Hey all, I'me trying to convert a C algorithm to Verilog using Quartus
II Web edition.
The following for loop doesn't compile because it says its not of
constant loop time.
What i really need is to be able to calculate the loop time "on the fly".
Can VHDL or Verilog do this? or is this ...how can I simulate the vhdl and verilog mixed design in modelsim?
Jimmy - 2004-08-28 10:40:00
Hi, all ,
I am using ISE6.2 and modelsim5.8b. My design is composed of two
modules, one is VDHL design ,and the other is verilog design. Now I want to
combine them together in a top level file (in vhdl) and simulate the whole
design. Can I just instantiate the verilog design module with a ...Question about filters and verilog etc..
Jan Panteltje - 2003-12-12 15:42:00
I need to make some filters now for some project in FPGA.
I was wondering if some free (open source?) software
exists that outputs verilog (or a xilinx module for example)
with as input say -3dB point, slope, poles, low / high pass etc.?
These programs do exist for analog filters, some from IC
...Is there a verilog version of PicoBlaze?
2004-06-17 05:39:00
Hi all,
I have downloaded a VHDL version of PicoBlaze. I can synthesize it
with other VHDL modules, my I prefer the use of Verilog, so the only
way I can use it with them is through EDIF black-box.
Anyway, life could be better if I can use a verilog version of
PicoBlaze directly. Does a...Getting started with VHDL and Verilog
2008-05-06 14:06:00
Hi all,
My background is in Software Engineering C,C++,Java and Unix. I am
getting started with VHDL and Verilog. What is the good way/books/
websites/training to get started? I have B.S. and M.S. in Computer
Engineering. Also, what is the learning curve in VHDL and Verilog?
Please let me k...Using Verilog to embed the synthesis date and time
John Providenza - 2004-07-19 11:27:00
Does anyone have a simple way to embed the date and time
that a module is compiled into a wire or register in Verilog?
I could use a Perl script to create an `include file with the
proper `define statements, but I'm wondering if anyone has
a cute way to do this purely in Verilog.
FYI - I'm ...why systemc?
2004-09-08 02:14:00
Hi,
Can anybody elaborate on the speed of the simulation in systemC in
comparision with Verilog. In our case we have used the systemC for
the modeling of RTL design, then verified the systemC RTL models. As
a final step
systemC RTL is converted into verilog RTL(line by line translation).
we ...Adding Verilog processing core to Viretx2Pro at ML310
sps - 2005-06-13 15:26:00
Hi,
I have a Verilog processing core. I want to implement it on Vertex2Pro
device as a separate core , adding it to current bus architecture. I
know that VHDL cores can be added.
Is it possible to add Verilog cores?
Thanks for the reply.
Regards
SPS
...Instantiating an lpm dcfifo in Verilog
jjlindula@hotmail.com - 2008-05-20 13:02:00
Hello, I know many will say this is not an appropriate group to post
such a question, but I wasn't getting any response on the Verilog
group, so please let me apologize. I am new to Verilog and need some
help instantiating a lpm dcfifo in my code. Here is what I have so
far:
FIFIN : ...Missing module : XFFT_V3_1 Verilog (not VHDL) module
Vitaliy - 2006-11-20 19:46:00
Hello,
Does anyone know if XFFT_V3_1 Verilog (not VHDL) module (normally found
in C:\Modeltech_xe_starter\xilinx\verilog\XilinxCoreLib_ver) exists? It
was not shipped with ISE7.1i (I have noticed a few people in newsgroups
asking similar question), I got the update from Xilinx site but still
...