Sign in
Search Comp.Arch.FPGA
fpga by Keywords
Altera | ASIC | CPLD | Cyclone | DCM | DDR | DSP | Ethernet | ISE | JTAG | Linux | LVDS | Microblaze | ML310 | Modelsim | NIOS | OPB | PCI | Quartus | RocketIO | SDRAM | Spartan | Spartan3 | SRAM | Stratix | Verilog | VHDL | Virtex | Virtex-4 | Virtex-II | Xilinx | XST
Ads
See Also
Virtex-4
Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.
We found 1241 threads matching ""virtex4" "virtex 4" "virtex-4""
You are looking at page 1 of 32.
The most relevant threads are listed first
Connecting Virtex2pro to Virtex4 via RocketIO MGT's
jason.stubbs - 2005-04-14 09:15:00
The following extract from the Virtex 4 RIO user guide states:
*/Serialization/*
*/As in Virtex-II Pro X devices, Virtex-4 also serializes and sends the
least significant byte first. This is opposite of the format Virtex-II
Pro devices used in sending the most significant byte first./*
Wh...
Location of Virtex4 ASCII pinout tables
2006-08-29 15:04:00
I go to www.xilinx.com, and click on "Virtex 4 FPGA" (on the left under
"Products")
This brings up the URL
http://www.xilinx.com/products/silicon_solutions/fpgas/virtex/virtex4/index.htm
At this URL, on the right, under "Related Information", there is a link
named "Virtex-4 package files"
...Trying to get plb_temac working
Benedikt Wildenhain - 2006-09-10 16:06:00
--vkogqOf2sHV7VnPd
Content-Type: text/plain; charset=us-ascii
Content-Disposition: inline
Content-Transfer-Encoding: quoted-printable
Hello,
I am using the XilinX Virtex 4 FX 12 Evaluation Kit and want to get
ethernet working (it will have to do some IP networking stuff). The board
is e...Re: help needed for Virtex-4
Jon Beniston - 2008-07-22 12:44:00
On 22 Jul, 17:41, "saad" wrote:
> Hello All.
> =A0 =A0 =A0 =A0 =A0 Can anyone tell me the Push buttons ,leds names that =
i can write
> in the constraint file for Virtex -4.
> Any code that helps me test the functionality of virtex 4 will be
> appreciated.
Which PCB are you using?
...Completed my first Virtex4 design
Philip Freidin - 2004-09-03 01:32:00
Well,
Xilinx shipped me my Foundation 6.3i software update,
and since it has the initial support for Virtex 4,
I installed it and did a design.
Here it is:
====
module top(in_bus,out_bus);
input [15:0] in_bus;
output [15:0] out_bus;
assign out_bus = {in_bus[14:0],in_bus[15]}...Re: Where to find very basic FPGAs
Sylvain Munaut - 2004-11-11 04:12:00
What about the Avnet Virtex-4 kit ?
http://www.em.avnet.com/evk/home/0,4534,CID%253D16863%2526CCD%253DUSA%2526SID%253DNoNav%2526DID%253DDF2%2526LID%253D4746%2526BID%253DDF2%2526CTP%253DEVK,00.html
299$ For a virtex 4 sounds ok. It's only 3x the price of the spartan3 starter kit and has lot...Re: Performance claims
Paul Leventis (at home) - 2004-12-08 20:21:00
I would like to offer some clarification of points raised in this
whitepaper, first in summary and then in some detail. I will occasionally
refer to our web-based performance seminar
(http://seminar2.techonline.com/s/altera_dec0704) for further details.
* Constraints. The clock const...Virtex4: Usign OSERDES + LVDS Deserializers
Roel - 2005-02-17 19:27:00
Hi
Has someone experience in using the OSERDES in combination with a
commercial Deserializers like MAX9206/MAX9208 or SCAN921226 ? I was
wondering whether it would be possible to meet the jitter requirements
and thereby preventing that the deserializer's PLL unlocks. I can' find
the right...virtex4 virtex-4 FX eval board
Pete - 2005-02-28 19:49:00
Hello
Is there a Virtex4 FX eval board available yet?
We want to begin working with the on-chip Gig Ethernet mac.
Pete
...Virtex 4 USER1 ~ USER4 JTAG commands
2005-03-10 04:20:00
Hello everyone,
I'm trying to use Virtex4 (Virtex4 LX25 Xilinx ML401 board) USER1 ~
USER4 JTAG commands from my software.
I have used my software to access such USER1, USER2 commands in
previous generation FPGAs such as Virtex-II.
Virtex 4 uses different JTAG command bit patterns (10 bit ...Chipscope and Virtex4 LX25 ES
John Williams - 2005-03-23 01:42:00
Hi,
Xilinx solution 20060 refers to the issue with the Virtex 4 LX25 ES
parts and the JTAG chains, with workarounds for the EDK's XMD and
opb_mdm tools. However, this silicon bug also affects ChipScope Pro,
but no solution is offered.
We are considering prototyping a large project on th...Virtex4 running at 360Mhz DDR
2005-05-10 14:48:00
I'm about to use Virtex 4, and wonder if this is achievable. All
literature seems to indicate that it is, but I'd like hear what others
think and perhaps point out where I need to be careful in the design.
I'd be receiving an LVDS clock pair @ 360Mhz, running part of the
internal logic at 360...EDK 7.1 XMD and platform USB cable
Antti Lukats - 2005-05-12 02:19:00
Hi
does anyone have had full success using the xilinx platform USB Cable and
XMD in EKD 7.1?
I was trying to check out the 'star wars' movie demo supplied by avnet with
their uClinux Virtex4 reference design, but unfortunatly my new PC has no
printer port so I am bound to use the latest and b...Virtex 4 MGTVREF pin reference circuit
jason.stubbs - 2005-05-17 11:25:00
There is a reference circuit for the MGTVREF pin on page 132 of the
Virtex-4 RocketIO MGT User Guide.
There is a resistor Refdes=R5 with a formula for calculating its value
as follows:
R5=(2.5v-VREF)/100mA where 2.5V is the pullup voltage, and VREF is
1.235V
I am assuming the 100mA is t...virtex 4 : how can I know the clock region coverage?
2005-07-13 16:37:00
Hi,
I know virtex-4 has 32 global clock lines and there is a requirement
that from any clock region, I can use up to 8 glock lines.
Is there any visualized way so that I can see what is the coverage of
each clock region for a particular chip? Or some table kind of listing
each clock regio...virtex 4 configuration error
2005-07-16 08:56:00
Hello.
I am trying to use the ML402 virtex4 (SX35) board and facing some
problems getting the FPGA to configure. I dont have a PC4 programming
cable, and am using the System ACE to do it for me. After i generate a
Bitstream (no errors), i put it on the Compact flash and let the system
ace p...Virtex4 : Downloading error
Shakith - 2005-08-31 00:25:00
I created microblaze design using bases system builder for virtex 4 lx25 lc board using Xilinx EDK 7.1i sp2.
After downloading, when using xmd to connect, the following error happens..
JTAG chain configuration -------------------------------------------------- Device ID Code IR Length Part Nam...ETHERNET MAC
ashwin - 2005-10-25 16:21:00
Hello Everyone,
I am doing a project on Implementing 10/100 ethernet mac on a fpga
using vhdl. I saw the link on fpga4fun.com, its implemented in verilog
and also i am not sure why he included ipaddreses and udp header. i
guess mac addresses of PC and fpga board should be sufficient.
I have m...Virtex4 temperature-sensing feature... does it work?
I. Ulises Hernandez - 2005-11-01 10:59:00
Hello guys,
Has anyone used the DXP and DXN pins in Virtex-4 yet? If so and if the
results were all right, what external sensor did you use...?
Thanks in advance,
--
Ignacio Ulises Hernandez
" I'm not normally a praying man, but if you're up there, please save me,
Superman!" - Homer ...Virtex 4 Configuration
Enzo Guerra - 2005-11-27 10:10:00
hello
have a few questions regarding the configuration pins on the V4 chip
1. in the Virtex-4 Configuration Guide [ug071].pdf, pg 35 figure 2-12, Note
1
1. The DONE pin is by default an open-drain output requiring an external
pull-up
resistor. A 330? pull-up resistor is recommended. In ...Successful use of MGT on Virtex 4
JarJarJP12 - 2005-11-29 15:41:00
Has anyone been able to successfully simulate a test of the MGT on the
Virtex-4? I've been trying to instantiate the GT11_custom for a while,
and it just does not seem to work. Basically I've instantiated two
MGT's and have tied them together via the RXN/P - TXN/P. I've tried to
use 8B/10B en...Power Optimization: can the routing and placement really save power?
Austin Lesea - 2005-12-28 17:06:00
Recently posted on our website:
http://www.xilinx.com/products/silicon_solutions/fpgas/virtex/virtex4/resources/Virtex-4_Power_Case_Study.pdf
Is a case study in which the latest claims of power savings by the
competitor's software are debunked.
I had intended to post this as part of the e...Virtex 4 desing : ChipScope insertion impacts my timing problem debug
2005-12-29 17:24:00
Hi,
I am working on a Virtex4 FX design, when the system clock runs at
100MHz, the memory controller core does not work correctly. Then I
inserted ChipScope trying to identify the problem, but once it is
inserted, the problem is gone!
I know it is of timing problem since if I lower the sy...PCI connection to PLB in Xilinx Virtex 4, what is required?
2006-01-06 02:38:00
I am starting a new design and would like to connect the Virtex-4
PowerPC to another external device with a PCI bus. The IP cores I find
on the Xilinx web site seem to suggest a connection from the PLB to the
OPB though a bridge, and then another bridge from the OPB to the PCI
bus.
Is this n...Virtex4 : Audio Codec AC97 LM4550
Lori Lorenser - 2006-01-30 08:00:00
Hi.
I'm working with the Virtex 4 on a ML403 and want to use the audio codec AC97. At first i want to connect a mp3-player to line in and then i want to manipulate the audiostream and send it to line out. But i don't find a detailled description (e.g not in ml403 userguide) of the audio codec. So...Virtex4 MGTs using Aurora Core
2006-03-02 04:35:00
Hi,
I am having problems trying to get an Aurora core working in Virtex 4
parts.
Has anyone managed to get an MGT working in Virtex4?
I am using Aurora 2.4 and just trying to do a simple loopback between
2 MGTs. I can't get CHANNEL_UP to assert in the Aurora cores and
the MGT is showing RX...Virtex 4 deconfiguring itself ...
Sylvain Munaut
Hello,
We're currently working on a design running on a Virtex4 SX35. That
design uses most of the resources of the FPGA (around 80% of the slices
and 50% or the BRAMs/multipliers). We're working on the AVNET SX35 kit
with a VGA extension card and a sdram expension card.
Depending of the da...Virtex4 FX12 dynamic clock divider
Guru - 2006-05-16 16:10:00
Hi everyone,
For my design, which is implemented in Virtex-4 FX12 (speed grade -10)
I need to get an adjustable (in operation) clock of frequency 30 to 66
MHz with the smallest possible increments. On the board I have 100MHz
oscillator from which I tried to get 400 MHz (the higher the frequenc...API on Virtex 4 FPGA or the email of Delon Levi wanted
2006-06-06 22:49:00
Hi all,
I'm making research on Hardware Evolution and has bought a
Development Board named DS-BD-V4LX25LC REVISION 2(VIRTEX-4 LC inside)
of Memec Design. I learned that Delon Levi developed the API on Virtex
4 FPGA, and i need it urgently on the academic research(i declare that
it would be ...Virtex 4 ACE Compact Flash configuration problem
Dan - 2006-07-18 18:31:00
I am trying to program Xilinx Virtex4 evaluation board ML402 via ACE using Compact Flash card. Every time when I turn the device on the red LED 'Err' turns on.
...Linear priority encoder in Xilinx Virtex4
Sylvain Munaut
Hello,
I need a linear priority encoder that has N input and N outputs.
Searching the group, I saw a thread where Peter Alfke stated :
--- cut ---
> Let me tell you what can be done in Virtex-4 (probably also in
> Spartan3):
> A priority "linear encoder" with 4 x N inputs and 4 x N ou...JTAG cable @ 2.5 V - where?
Markus Zingg - 2006-10-03 09:13:00
Hi group
I'm a newbee, so please bear with me if this does not make sense.
I got a AVNet (MEMEC) Virtex 4 based developper kit based on the
Virtex-4 FX12 Mini Module whoes baseboard JTAG port is documented as
"a 2.5V compatible JTAG chain header". The pinout is identical to what
Xilinx see...Virtex 4 SX, Dedicated Configuration pins
Anastasios Salis - 2006-10-09 12:54:00
Hi eveyone,
I am designing a schematic for a project using Virtex-4 35 SX, and a platform flash for configuration (XCF16PVO48C). For the FPGA I use VCCO_0 = 3.3V, VCCAUX = 2.5V, and VCCINT = 1.2V. For the platform flash I use VCCO = VCCJ = 3.3V and VCCINT = 1.8V.
I want to use a 3.3V Jtag inte...Virtex-4 configuration details
jbnote - 2006-10-10 11:54:00
Hello,
I'm currently looking at the virtex-4 configuration details and have a
question about FDRI writes in the virtex4.
My reference point is the virtex-2 configuration. In the virtex-2
configuration, FDRI writes always include a pad frame (except in the
MFWR write case, but that's not wha...Virtex 4 RAMB16 Clock: optional inverter missing
Frank Leischnig - 2006-10-11 10:23:00
Hello,
The RAMB16 component has much less clock-to-out time when using the
optional output register. However, I need valid data one clock cycle after
the address input is valid.
The Virtex-4 User Guide ug070 states in Figure 4-5 (Page 115) that there
are two optional inverters in the clo...Coregen GMII embedded ethernet MAC
Rune D. Jørgensen - 2006-10-12 11:55:00
I have been trying to implement Virtex-4 Tri-Mode Embedded Ethernet MAC
Wrapper v4.3(GMII) from coregen in ISE. All guides tell me to use a VHO-
file, which should contain an instantiation template, but coregen doesn't
create such template file for this core. And the template in ISE is blank.
...XPS crashes while performing clock DRCs when I have DCR components instantiated
Jeff Cunningham - 2006-10-25 00:56:00
I am using XPS 8.2.01i to create a V4FX12 design for the the xilinx
ML403 board. I used bsb to create a design with a 300 Mhz PPC, a 100 Mhz
PLB and the PLB_DDR interface. No internal block ram. It got that to
build just fine, after figuring out to comment out a line in
etc/fast_runtime.opt ...Supported bus widths for RLDRAM on Virtex4?
Your name - 2006-10-25 03:57:00
Hi there,
I'm trying to decide on which FPGA vendor to use for a project out of
Xilinx and Altera. The one we chose will depend on a certain memory
bandwidth being met so I'm interested in the maximum supported bus widths.
I'm currently heading down the RLDRAM route and have been trying t...Re: Chipscope and debugger through the same JTAG port
Joseph Samson - 2006-10-30 14:06:00
MM wrote:
> Joseph,
>
> I might have had a few timing errors, which could affect some of the
> channels but not all... What kind of cable (USB, parallel, etc.) are you
> using and what chip/CPU combination?
Parallel Cable IV running under XP, connecting to Virtex2Pro, Virtex4
FX60 and ...Tsamp for Spartan 3?
Nick - 2006-11-02 05:17:00
A while ago Xilinx introduced the parameter "Tsamp" into the Virtex 4
data sheet, described as:
"TSAMP Sampling Error at Receiver Pins
This parameter indicates the total sampling error of Virtex-4
DDR input registers across voltage, temperature, and process.
The characterizati...