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Virtex-II
Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.
We found 1362 threads matching ""virtex ii" "virtexii" "virtex-ii" "virtex2" "virtex 2""
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Infiniband via RocketIOs (RocketIO, Rocket IO) on Virtex 2 (Virtex2, Virtex II, Virtex-II)
Bruce - 2004-08-13 09:09:00
Hello,
at present I am working on an Infiniband implementation on a Virtex-II
Pro. As far as I know the build-in RocketIOs are fully compliant to
the Infiniband standard (beacon and variant CRC excluded). There are
two types of CRC, the invariant and the variant type. Although the
RocketIOs are...
Infiniband
Bruce - 2004-08-13 09:40:00
Hello,
at present I am working on an Infiniband implementation on a Virtex-II
Pro. As far as I know the build-in RocketIOs are fully compliant to
the Infiniband standard (beacon and variant CRC excluded). There are
two types of CRC, the invariant and the variant type. Although the
RocketIOs are...Starter Kit for Linux in Virtex?
Frank Benoit - 2004-06-15 06:53:00
Hi
I want to build an application with linux running in
virtex2pro with ethernet and usb. Now I want to calculate. How much, do I
have to invest? For this calculation I have to know which components I
need.
Can anybody give me a hint? Which evaluation board is best, to evaluate
linux in V...Virtex 2 with PLB_v34 and EDK 10.1
rmeiche - 2008-05-28 09:17:00
Hi,
I'm trying to build a system for a XC2V6000 FPGA. The problem I have
is that I have to implement a PLB. But the PLB shipped with the EDK
10.1 is the PLB_v46 which doesn't support the virtex II, only V2Pro
and V4.
At the datasheets on the xilinx website I found that the PLB_v34
should s...Re: Regulator for Spartan 2
Paul Leventis - 2003-09-29 23:34:00
Hi Jon,
> Well, he's certainly using the right (read ONLY) architecture that will
> do it.
> I got started with Xilinx on a project where I needed 72 flip-flops on a
> board, all essentially asynchronous from any other. (This was a timing
and
> logic controller for nuclear detector app...Signed Multiplication in a Virtex-II Multiplier.
Anil Khanna - 2003-10-17 18:15:00
I am trying to construct a 6x6 signed multiplier using the Virtex II block
multipliers. I know that the V-II multipliers are inherently a 2's
complement signed multiplier. However, my question is - by how much should I
sign-extend the inputs?
Example:
Input A - 6 bit
Input B - 6 bit
Output ...jitter in Virtex2 DCM
Tullio Grassi - 2003-11-30 11:06:00
The VirtexII data sheet requires an input jitter for
the DCM smaller than + or - 300 ps (in Low Frequency Mode).
Obviously this ensures the proper behavior across all
permitted frequencies and modes.
In my case I have an input clock with 1ns of pk-pk jitter, but
it is a 40 MHz clock, that I ...Re: How to generate a CSA tree?
Uwe Bonnes - 2004-01-13 05:30:00
Sleep Mode wrote:
: Hi all,
: I am trying to design a 16-bit integer multiplier in VHDL and I want to use
: a Carry-Save-Adder (CSA) tree for generating the interim subproducts
: and -then- with an additional CPA (or other) adder to add them to the final
: 32-bit product; i.e. I want to bu...Virtex II - LVDS_33_DCI?
Barry Brown - 2004-01-14 12:45:00
In the Virtex II User Guide (v1.6.1) on pg 200, it states ...
DCI in Virtex-II Hardware
DCI only works with certain single-ended and differential I/O standards. DCI
supports
the following Virtex-II standards:
LVDCI, LVDCI_DV2, GTL_DCI, GTLP_DCI, HSTL_I_DCI, HSTL_II_DCI, HSTL_III_DCI,
HSTL_IV...Virtex 2 Fastest MUX performance
Adam - 2004-02-09 13:55:00
On the bottom of page 7 of the Virtex II DC and Switching Characteristics
datasheet, a table shows that register-to-register performance of a 4:1 mux
can reach 563 MHz. I'm just curious exactly how this was measured.
Thanks,
Adam
...Virtex2 (500) DCM Frequency Synthesize
Jerzy - 2004-05-07 10:49:00
Hello
I've got following problem:
I need 27MHz and 54MHz clocks, input freq. is 20MHz.
Till today I used DCM FS 27/20 next to DLL and DLL*2.
Theoreticly it should works OK, but doesn't. From time to time after
reboot or after clok stop, it works strange and completly bad. Today
I've read about...Re: synthesising VHDL for Xilinx FPGAs using ISE 6.1i
Mario Trams - 2004-05-13 07:41:00
Michael,
> > Most FPGAs (so the Virtex) have tristatable drivers and can handle
> > real busses.
>
> As I remember there are no real tristate signals any more in Xilinx
> FPGAs because they were too slow ... real tristate is only in the IOBs
>
> in the FPGA there are structures that...Re: Request for 28 BIT ADDER maximum clock rates for Virtex II FPGAs
John_H - 2004-08-11 18:26:00
80 MHz is extremely slow and easily achieved in any FPGA introduced in the
last several years. I would expect that 200 MHz is easy in the slowest
speed grade of Virtex-II but I haven't bothered to run the numbers.
"Bill Hanna" wrote in message
news:97d137ce.0408111414.1d4f1011@posting.go...linux on virtex 2 pro board
rajendra k singh - 2004-08-17 15:36:00
Hi All,
I am trying to boot linux on virtex 2 pro P7-ff672 board. My problem is
that I am able to boot the linux image(ppc) on bitstream generated by EDK
6.1 but not with bitstream generated by EDK 6.2 (SP2). Does anyone had
similar experience ? I wonder if the problem is EDK 6.2 or I need t...Virtex II LVDS plus DDR?
Mark - 2004-08-20 17:43:00
Howdy Gurus,
I've seen the Xilinx Virtex 2 IOB documentation describing their LVDS
i/o and their DDR i/o, but haven't found a clear explanation yet of
the two being used together.
DDR by itself is pretty obvious, but the LVDS appears to work by a
magical connection between two neighboring I...Re: Virtex 4 released today
IgI - 2004-09-14 17:03:00
Hi!
A Xilinx representative came today to the company where I work and he had a
short but very informative Virtex4 presentation. What I find very useful is
that Xilinx finally put a FIFO control logic on BRAMs and significantly
increase their performance. Feature to cascade FIFOs will also be ...Virtex2 I/O standards
gja - 2004-12-14 23:21:00
For Virtex II parts, I see that the Vih and Vil levels are the same for
LVTTL and LVCMOS33, my question is are the input structures really different
or are they the same for the two standards. Also, are the output structures
for LVTTL the same as LVCMOS33, since both Vol are the same, and LVT...Re: Hardened Logic and SEUs
Austin Lesea - 2005-01-20 18:28:00
Ben,
Well, based on the numbers I gave, V2P has a higher FIT/Mb rate than V4,
but generally speaking the V2P chip folks use is smaller (less memory
cells, less logic) than the V4 chips.
So, at one time the sweet spot part for Virtex was a XCV300.
Then for the Virtex E it went up to a XC...lwip on spartan3
adrian - 2005-02-26 07:58:00
Hi there,
I am trying to design a network application on a Spartan 3 Starter Board
with an ethernet module incorporated using lwIP.
In the past I have managed to run network applications on Virtex II Pro
boards based on xilinx application note xapp663.pdf "TCP/IP on Virtex-II
Pro Devices U...Downloading problems [Memec DS-BD-V2MB1000 Virtex-II board].
Henrik Koksby Hansen - 2005-03-18 05:51:00
Hi,
I am using JTAG Cable IJC-2 from Memec and Xilinx Platform Studio
(Xilinx EDK 6.3 Build EDK_Gmm.12.3+1) to program subj.
Typically in the morning, the programming fails constantly until it
suddenly works after an hour or two. When it then works, it keeps
working. For that reason i belei...Avnet Xilinx Virtex-II Pro Development Kit
Mindroad - 2005-03-18 15:09:00
board : Avnet Xilinx Virtex-II Development Kit
fpga : Xilinx Virtex II Pro 20 ==> 2 ppc405, and so on ...
problem : avnet includes a ucf file for this FPGA stating the physical
pinning for an externally attached ddr sdram of 128MB
With Base System Builder Wizzard in EDK/XPS I create a design ...DDR SODIMM on Avnet Virtex II PRO development kit
ZioPino - 2005-04-23 08:00:00
Hi all,
I'm working on a ADS-XLX-V2PRO-DEVP20-6 (The Xilinx Virtex 2 PRO
development kit from Avnet, with a XC2VP20 onboard), and I was wondering
if it was possible to connect the DDR SODIMM module (the board comes
with a Micron 128 MB module) to a Xilinx EDK 6.3 design with plb_ddr or
opb_...TRACE and Modelsim Timing Help
GianniG - 2005-05-09 09:47:00
Dear Gurus,
I hope that someone would help me on how to interpret the following
timing parameters. Thank You very much in advance.
I have to interface an ADC to a VirtexII-4 Board, 16 bit data + 1 clk;
both data and Clk are LVPECL. I have successfully implemented such
interface at a frequen...How to get *.mcs file containing both *.bit and *.elf file, to port linux on my memec virtex-ii board.
beomseok,lee - 2005-06-04 06:51:00
Hello
I have 'Virtex II pro FF1152 board, Rev.3' made by Memec design.
I read the document 'Getting Started with EDK and Montavista Linux'.
http://www.xilinx.com/bvdocs/appnotes/xapp765.pdf
And I followed the directives in the document. but I had a trouble.
In the document, I shou...Simulation problems virtex II
zoinks@mytrashmail.com - 2005-06-07 07:39:00
Hi everyone,
I have been trying to get a good behavioral simulation going of a
Virtex2 on the ML310 board. I'm trying to simulate a standard generated
chip architecture with DSOCM & ISOCM running the standard generated
test-program.
As far as I know there are two ways to go (with the ...Xilinx PLB IPIF Master
Eli Hughes - 2005-10-06 16:40:00
Hello:
Has anyone actually gotten the master functionality in the PLB IPIF to
work correctly? I have been making slave peripherals without a problem.
I have an application where I am trying to directly transfer 64-bit data
from my peripheral to DDR ram. This problem came about as the Powe...Malloc on PowerPC on VirtexII pro
Tibo - 2005-11-07 08:45:00
hi,
I'm using a PPC405 on a Virtex2 pro. I try to allocate memory
with malloc() function. It compiles without any problem but malloc
returns NULL => no memory is allocated. I set the heap size at 0x0800 in
docm. I set need_xil_malloc to false since xil_malloc seems to be used
only for Micro...Question on 2048 point FFT( Basic)
aj - 2005-11-23 02:13:00
Hello FFT guru's
I am implementing 2048 point FFT on Virtex as a part of my small
project at uni. i want to put couple of questions.. please help me to
your best as i am a starter...:)
I have gone through couple of IEEE papers and i have found that i
should use (Mixed Radix alg).i.e. like R...virtex II global buffer
zora - 2005-11-23 12:16:00
Hi
I need to use more than 8 global buffer in a virtex II design.
I know that VirtexII supports up to 16 Global Buffer divided in more
clock regions, but ISE PAR doesn't automatically divide project in
two (or more) clock region and it uses only 8 global buffer. How can
I use the other global buffer...Virtex 2 configuration problem
gja - 2006-01-04 21:23:00
I'm looking for some suggestions as to what else to look at to fix this
problem:
Using a Virtex II xc2v40 and xcf02s prom connected in master serial mode.
JTAG is also implemented. We've built around 50 of these boards without
this problem so I believe it's just this particular board. It ...Virtex2: can I really just leave M1,M2,M3 pins floating?
ML - 2006-02-21 14:37:00
Hi all, for a Virtex II part, for slave serial mode, can I REALLY leave M1,
M2, M3 pins floating or is it safer to tie them to VCCaux ?
ML
...Anyone with Insight DS-V2LC Board Rev. 2 datasheet?
Frank - 2006-02-28 21:43:00
Hello everybody:
I was given this board but I can not find the datasheet of it. It has a
Virtex II device (XC2V1000FG256) on it. Next to Insight Xilinx logo
there printed Virtex-II LC Board Revision 2 May/2001 JBE/JBE.
Anybody has this datasheet and can drop me an email at
kelvin_xq@yah(rem...Files.ucf QAM Demodulators for Xtreme DSP Development KIT
vlir_c8 - 2006-05-14 22:47:00
Hello everyboby,
My name is Giovanny
I am working with two types of xtreme dsp Development cards: Kit virtexII
( xc2v3000) and virtex II
PRO (xc2vp30) ;
I am trying to implement the example "16 QAM demodulator for Software
Defined Radio" running sysgenqam16_dplr.mdl file in simulink ;I...ModelSim: Different SimPrim libraries needed for different Xilinx families?
Jon - 2006-06-01 11:38:00
Hi there,
I've just left a computer compiling the SIMPRIM libraries used by
ModelSim for Low-Level (post place and route) simulation (I started
this using the "Compile HDL Simulation Libraries" process in the ISE
software).
When the process started, I noticed it said the following:
Sched...virtex II inner organisation
flo - 2006-08-12 16:21:00
Hi everyone,
I'm trying to deal with readback and scrubbing into a XC2V1500 FPGA.
I've got a problem identifying the Major Adress and the Minor Adress
when I'm doing a readback.
I read documents (XAPP138 and XAPP151) but nothing works with virtexII.
I know the frame length and the number of ...problems with IOSTANDARD
Martin Geisse - 2006-09-15 07:49:00
Hi to all,
I'm trying to set the output voltage level of a Virtex 2 pro using the
IOSTANDARD constraint, but it doesn't work.
More exactly, I'm using the XUP Virtex-II Pro Development System (an
evaluation board) by Xilinx. For an application, I need the FPGA to
output 3.3 V signals on the ...Re: Spartan3E and DDR termination
vasile - 2007-09-05 10:55:00
On Sep 4, 1:42 pm, Gabor wrote:
> On Sep 4, 3:40 pm, vasile wrote:
>
>
>
>
>
> > On Aug 30, 8:41 am, Gabor wrote:
>
> > > On Aug 30, 9:41 am, Gabor wrote:
>
> > > > On Aug 30, 4:59 am, Guru wrote:
>
> > > > > Hi all,
>
> > > > > We are build...Re: Help with a face recognition system
Matthew Hicks - 2007-03-31 03:23:00
We (Illiac 6 research group at the University of Illinois) are currenlty
working on porting one of the more popular face recognition programs for
an application that is going to run on our "Communications Supercomputer",
which involves a Virtex II-Pro FPGA. These is no benefit from implementi...Using PCI in EDK 8.21
2007-04-25 00:53:00
Hi,
I have been trying to use the OPB PCI bridge in EDK 8.2. So far I have
not been able to synthesize it properly. I am using a custom board
with Virtex II, I include the PCI bridge during the BSB wizard. Is the
assembly view, I configure the IP to be used as a target. My first
milestone is to...Using OPB PCI Bridge in EDK 8.2i
2007-04-25 01:10:00
Hi,
I have been trying to use the OPB PCI bridge in EDK 8.2. So far I have
not been able to synthesize it properly. I am using a custom board
with Virtex II, I include the PCI bridge during the BSB wizard. Is the
assembly view, I configure the IP to be used as a target. My first
milestone is to...