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Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.
We found 1126 threads matching "xst"
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The most relevant threads are listed first
Synplify vs XST...
Austin Franklin - 2005-06-11 15:39:00
I have not use XST, but it is becoming more attractive. I have been using
Synplify for many years now, and it works pretty well. XST has come a long
way, especially now that it appears to have an RTL viewer as well as a
"implementation" (gate level) viewer, which are two features I liked about
...
Does XST support global signals?
EM - 2008-09-26 16:15:00
Hello folks,
I searched this newsgroup, Xilinx's website, and the XST user's guide,
but I couldn't find what I was looking for.
Does anyone know if XST supports global nets?
In my last project I used Synplicity, which allowed me to use global
nets / buses. In this new project I'm using...xst synthesis
brassaro@iro.umontreal.ca - 2005-11-16 16:19:00
Hi,
I am having problems with XST Synthesis from Xilinx. When synthesizing
a unit from my created IP, the synthesis tool just stops, providing no
error explanation. The last messages I get from the log files are the
following:
Synthesizing Unit .
Related source file is
//hamurabi.iro.um...XST Question
Naimesh - 2004-11-07 22:20:00
How do I buffer a signal in XST as I feel it is getting overloaded.
if I write
Signal1 ...XST and TCL support?
Brandon - 2005-07-28 13:50:00
Does XST 7.1 support TCL scripting?
I don't see any mention of it in the XST User Manual and I find the
command line mode to be very awkward performing synthesis using the GUI
or command line without a script.
I'm new to XST, and I'm looking for ways to organize my synthesis
process. By def...XST and Verilog $readmemh
johnp - 2007-04-11 21:32:00
In theory, XST claims to support the Verilog $readmemh to initialize
memory. I'm
using the latest 9.x s/w verion.
I look at the .syr output file from XST, and it claims to have read
the file. But...
If I hook a logic analyzer up to the output of the memory, it looks
like it never got
in...Xst Error
Ramakrishnan - 2005-12-14 18:07:00
Hi, I was trying to implement my design in Xilinx ISE using Xst as the Synthesis tool. It gave me a error INTERNAL_ERROR:Xst:cmain.c:3020:1.146 - To resolve this error, please consult the Answers Database and other online resources at . To give you a basic idea, my program is IF Generate Structure...Xilinx XST 6.x and Verilog-2001?
Allan Herriman - 2003-09-30 01:42:00
Hi,
Does Xilinx XST 6.x support RTL-synthesis of Verilog-2001?
This document
http://toolbox.xilinx.com/docsan/xilinx5/data/docs/xst/xst0083_11.html
shows that the older version, XST 5.x, has partial support for Verilog
2001.
I was wondering if the support is better in the newer version o...Got the XST (ISE8.1) EQUIVALENT_REGISTER_REMOVAL blues
Morten Leikvoll - 2006-03-21 10:18:00
-Ive tried unchecking the EQUIVALENT_REGISTER_REMOVAL property in xilinx
specific options,
-Ive tried the KEEP attribute
-Ive tried BOTH at the same time
-Ive tried portmapping to FDCE
-Ive verified that the xst file contains -EQUIVALENT_REGISTER_REMOVAL NO,
-Ive tried googling on this issue ...Define the primary clock with XST in VHDL
Julien Lochen - 2008-02-18 09:17:00
Hello Guys,
How to specify with XST that an input of a VHDL entity is a clock ?
I guess it is not automatic because after the XST logic synthesis,
noone of my "process" have been synthetized ?
thanks, Julien
...warning from ISE 9.2
Thorsten Kiefer - 2008-05-06 11:29:00
Hi,
waht does that mean :
Loading device for application Rf_Device from file '3s200.nph' in
environment /home/thorsten/Xilinx92i.
WARNING:Xst:2677 - Node of sequential type is unconnected in block
.
WARNING:Xst:2677 - Node of sequential type is unconnected in block
.
WARNING:Xst:...Help, i'm geting warnings :-(
Mr M - 2005-02-03 11:30:00
I’m wondering. I wrote the following VHDL-code (this is only an example, not
something usefull):
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter_test is
Port ( clk : in std_logic;
cn...XST vs Synplify
2005-11-23 05:31:00
Hi all,
I wish to have an idea about how many people here uses Synlify or
Leonardo and how many people uses XST.
The purpose of that is undesrtand how many people here beleave that XST
is a mature product and it can be trusted or not.
At moment I'm tryng to use XST for a small FPGA (spartan 2E ...xst fails...
Matthias Alles - 2007-08-14 05:31:00
Hi,
I'm currently trying to synthesize a big design on a Virtex4-VLX100. Now
the problem is, that xst fails and just gives the following line:
Process "Synthesize" failed
Is there a way to hunt for the problem that causes this behavior? I'm a
little bit lost, since there is no hint by xst...XST 3.0 Xess Audio to Ethernet
Scutum612 - 2008-05-25 05:38:00
Im a beginer in VHDL and i got some problems regarding Ethernet usage
on XST 3.0 Board. I want to send audio trought ethernet to a second
XST 3.0 but i have a lot of problems regarding Ethernet interface
initialization - I'm not able to sent anything. I will meke some
package processing later on...Serious problem with XST
Matthias Alles - 2006-02-27 03:23:00
Hi,
I encounter a serious problem with xst when I try to synthesize a
design. The design consists of several components that synthesize fine
for themselves. However when I want to synthesize the top entity, that
only plugs the simple components together, xst fails during the low
level syn...Re: Is this phase accumulator trick well-known???
Brian Drummond - 2009-02-09 19:13:00
On Mon, 09 Feb 2009 19:03:01 +0000, Jonathan Bromley
wrote:
> let's see what the bug report should look like...
>
> Dear Xilinx,
> XST compiled my code exactly the way I wanted it.
> Please fix XST so that it will NOT compile my code.
> Yours sincerely,
> A. Masochist...XST options in XPS
brassaro@iro.umontreal.ca - 2005-11-21 12:55:00
I am using XPS to synthesize a Microblaze system with custom hardware
functions connected with the FSL bus. The synthesis of the design is
done by XST, which is launched from the XPS.
I was wondering if there was a way to give options to XST for the
synthesis, and if yes, where to specify them.
...XST design frequency setting
2008-04-17 13:22:00
Hey everybody,
Just started using Xilinx XST as my synthesis tool and I'm just
looking for the command line instruction (or GUI) to set the design
frequency, I was using precision where it was "setup_design -
frequency=66".
Anyone know the equivalent command for XST?
My eyes cant seem to...XST removes duplicate logic no matter what
MM - 2009-03-31 17:10:00
I've been fighting XST not to remove duplicate logic I put on purpose to
decrease fanout on some nets and I can't find a set of attributes, which
would work... I tried "keep" and "noreduce" in combination with MAX_FANOUT,
but XST(8.2.03i) seems to just ignore them all. Does anyone know how to ...Generics of type time and XST synthesis
Brandon - 2005-07-20 11:34:00
I'm new to FPGA synthesis and XST, so I could use some help.
I'm synthesizing an entity for the first time, and I'm receiving
warnings and errors related to the time type in my models. I realize
that they are not synthesizable. I'm okay with the warnings because I
have them in there for functi...XST issues with loop code
Jeff Brower - 2006-04-19 10:53:00
All-
I had posted before about XST not generating correct netlist for
comparisons inside nested loop code within an always block. The code
is of this form:
always @( a[0], a[1], a[2], ... ) begin
for (i=0; i ...Question for XST expert
Laurent Gauch - 2004-10-20 07:12:00
Hi all,
I am finishing my PCI core.
I want to do from XST an .ngc file of my PCI core.
The goal is to map IO buffers for all the PCI signal and to let other
signals without IO buffer mapping.
If I use the XST command line -iobuf , I can only enable or disable the
use of IO Buffer on al...never seen XST error
john wo - 2005-06-13 12:52:00
what about this error?
--------------------------------- INTERNAL_ERROR:Xst:cmain.c:3022:1.146.4.1 - To resolve this error, please consult the Answers Database and other online resources at ERROR: XST failed Process "Synthesize" did not complete.
xilinx.support and google gave nothing... wh...XST pre-defined macros
Jeff Brower - 2006-04-21 16:15:00
All-
Does XST provide any pre-defined macros or constants? For example:
__BUILD_NUMBER
__XST_VER
that could be used in source code as contents of a logic revision
register, or could be used to know which version of XST is in use?
If this is not available, is there a way to kludge ...ISE 10.1 XST runs in background?
emeb - 2008-03-28 12:08:00
Hi,
I installed ISE 10.1 the other day and just tried it out for the first
time this morning. I run my synthesis jobs on a Linux x86_64 machine
and use home-made make scripts to manage the build process. I noticed
that my make process completed too quickly, but that XST (the first
part of the...how to get XST to infer 8:1 mux or just hard code it?
Matthew E Rosenthal - 2004-04-07 04:05:00
I am trying to get XST to infer an 8:1 or even a 4:1 mux, instead of using
several 2:1 muxs'.
Is there a suggested coding style to get xst to infer the larger muxes or
how would i hardcode them to make larger muxes?
Thanks
Matt
...XST 9.1 hates VHDL character types
Andy Peters - 2007-03-09 14:53:00
Under ISE 7.1, I did a simple UART module that has a "terminating
character" generic, which is of type character. (When the receiver
sees that terminating character, it asserts a "got terminator" output
flag.) XST compiled it and the design works well.
I moved to 9.1, and now XST hates the c.../* synopsys enum state_code */ on XST???
2007-03-12 12:45:00
The /*synopsys enum state_code*/ constraint is pretty handy to handle
the FSM state encoding.
Unfortunately XST doesn't seem to be managing it correctly (as opposed
to
other synthesisers). Not reporting errors but breaking the FSM!
Anybody has a workaround?
I have a design I want to convert to...Re: Inferring Xilinx RAM's with Byte enable options
Duth - 2007-01-28 22:29:00
HI Anil,
If you are using 9.1i XST, the XST user guide examples of how to infer
byte enables.
This is only supported in XST starting in ISE 9.1i. The older versions
do not support this.
HTH
Duth
On Jan 26, 5:59 pm, "anil" wrote:
> Hello all,
>
> does any one have a...Xilinx XST synthesis removes input pin even though it's LOCed
Matt Dykes - 2004-06-17 16:51:00
XST keeps removing some of my input pins. I have used the LOC
attribute in both the VHDL itself and in the .ucf file to no avail.
After PAR, the pins declared in the port declaration (and LOCed to
specific pins) have not been routed to a pad.
The inputs ARE used by latching into a register t...Help with XST warnings (2)
morpheus - 2005-03-01 19:21:00
Can anybosy help me with these warnings? I tried looking at XILINX
answers database and found no record of them.
Moreover, I found out that by modifying the environment variable, these
warnings can be turned off....but i'm kinda skeptical as i dont know if
these are major show-stoppers or not
...XST corrupts my state machine. Only disabling FSM encoding helps
heinerlitz@googlemail.com - 2007-09-26 08:39:00
Hi,
i have a state machine like this
always @( * )
case(state)
IDLE:
casex(SOME_STATEMENTS)
{inputs}:
next = NEXT_STATE1;
{inputs}:
next = NEXT_STATE3;
default:
next = IDLE;
STATE1;
casex(SOME_STATEMENTS)
{inputs}:
next = STATE2;
{i...Restricting XST parameter widths from .mpd files?
Neil Steiner - 2007-07-28 20:17:00
I'm working with a custom verilog core that accepts a small number of
parameters, and I'm having a hard time pushing them through XST properly
under EDK 8.1.
For example, I include the following line in my .mpd file:
PARAMETER C_DCR_BASEADDR=0b0001000000, DT=STD_LOGIC_VECTOR, BITWIDTH=10, ...set dont touch in Xilinx Xst
Serkan - 2009-06-19 10:49:00
Is there a "set_dont_touch" equaivalent version of Xilinx Xst
attribute. Or is it only in synopsys?.
...XST -vlgincdir
Dave Colson - 2005-04-08 13:37:00
Hi,
Does anyone know what this switch really does?
They don't explain as to what is in that directory.
Does it mean that if you have an "`include" directive
in your verilog code that XST will search that directory for
the files?
Thanks
Dave Colson
...XST Timing report
Muthu - 2003-10-13 01:52:00
Hi,
I am using ISE5.1i...XST synthesis tool.
At the end of synthesis, XST generates defualt timing report for 1 or
2 paths.
How can i generate a timing report after synthesis for more than 100
paths?
ie., as like .twr after Place and route.
And How can i measure the time dealy betwe...ISE 7.1i incremental synthesis
2005-09-19 13:09:00
I'm trying to get incremental synthesis working with the Xilinx tools,
ISE 7.1i. I applied the most recent service pack, 7_1_04i_lin.zip
which was supposed to fix a fatal bug with this feature. However, I
still cannot get it to work. Has anyone had any luck with this?
My .xst file contains ...Re: XST bug on illigal states of a FSM ?
Jochen - 2008-09-03 11:15:00
XST-Guide:
"XST can add logic to your FSM implementation that will let your state
machine recover
from an invalid state. If during its execution, a state machine enters
an invalid state, the
logic added by XST will bring it back to a known state, called a
recovery state. This is
known as Sa...Re: Why cant XST sythesis this piece of code
RCIngham - 2008-07-14 10:02:00
>
> When running XST then XST is analysing an entity for ages that contains
> the following piece of code.
>
> if (signal1 = '1')
> for I in 0 to 15 loop
> if (signal2(I) = '0') then
> Table0(conv_integer(Table(I)) end if;
> end loop;
> end if;
>
>
> ...