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Comp.Arch.FPGA | configuration for a mixed mode VHDL-verilog lang
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configuration for a mixed mode VHDL-verilog lang - Rakesh YC - 2004-07-09 04:05:00
Hi all My problem is I'd like to choose a VHDL file instantiated inside verilog via VHDL configuration To summerize: I have a hierarcy: "top:vhdl - verilog - Verlog -vhdl: bottom" How to write a vhdl configuration to select the file for the bottom instantiation? Rakesh YC______________________________
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Re: configuration for a mixed mode VHDL-verilog lang - guhaoqi - 2004-07-09 06:16:00
try______________________________
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