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Comp.Arch.FPGA | How to extend a pulse width without clock in CPLD!
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How to extend a pulse width without clock in CPLD! - peterzhu - 2003-09-04 02:13:00
Due to a chip bug, I have to extend a pulse width(negative)from 10ns to 100ms in CPLD(Altera 7128). But the difficult is that I have no any clock into the CPLD, so the CPLD is pure combination logic. how to extend it in such case? Help me!______________________________
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