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Comp.Arch.FPGA | Virtex 4 released today
There are 51 messages in this thread.
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Virtex 4 released today - Austin Lesea - 2004-09-13 14:32:00
All, As Peter would say, the teasing is over: V4 is ALIVE. http://www.xilinx.com for all of the details. Now I can finally talk about it. Austin______________________________
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Re: Virtex 4 released today - Jim Granville - 2004-09-13 17:15:00
Austin Lesea wrote: > All, > > As Peter would say, the teasing is over: V4 is ALIVE. > > http://www.xilinx.com for all of the details. > > Now I can finally talk about it. .. and one of Austin's shortest posts ever ... ;) -jg
Re: Virtex 4 released today - Austin Lesea - 2004-09-13 17:59:00
Jim, Thanks for the encouragement, (long-winded, who me?) Austin Jim Granville wrote: > Austin Lesea wrote: > >> All, >> >> As Peter would say, the teasing is over: V4 is ALIVE. >> >> http://www.xilinx.com for all of the details. >> >> Now I can finally talk about it. > > > .. and one of Austin's shortest posts ever ... ;) > > -jg >______________________________
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Re: Virtex 4 released today - Jim Granville - 2004-09-13 19:06:00
Austin Lesea wrote: > Jim, > > Thanks for the encouragement, > > (long-winded, who me?) You're welcome :) To give you a chance to wind up on Virtex-4, here are a couple of questions : Virtex-4 does not seem to be supported in WebPACK - when is this planned ? Virtex-4 seems only available in large, BGA packages. When do we expect to see Spartan-4? in TQFP and anything < 360 pins ?. Xilinx has a nice Spartan-3 Eval PCB for $99, what is the Virtex-4 EvalPCB status ? ( $99 ? :) -jg______________________________
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Re: Virtex 4 released today - Kevin Neilson - 2004-09-13 23:12:00
"Jim Granville" <n...@designtools.co.nz> wrote in message news:dKp1d.3374$m...@news02.tsnz.net... > Austin Lesea wrote: > > Jim, > > > > Thanks for the encouragement, > > > > (long-winded, who me?) > > You're welcome :) > > To give you a chance to wind up on Virtex-4, here are a > couple of questions : > > Virtex-4 does not seem to be supported in WebPACK > - when is this planned ? > > Virtex-4 seems only available in large, BGA packages. When > do we expect to see Spartan-4? in TQFP and anything < 360 pins ?. > > Xilinx has a nice Spartan-3 Eval PCB for $99, what is the > Virtex-4 EvalPCB status ? ( $99 ? :) > > -jg Whoa; you can't expect the paperback to come out at the same time as the hardcover. -Kevin______________________________
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Re: Virtex 4 released today - Jon Beniston - 2004-09-14 07:31:00
Austin Lesea <a...@xilinx.com> wrote in message news:<ci4p3r$i...@cliff.xsj.xilinx.com>... > All, > > As Peter would say, the teasing is over: V4 is ALIVE. > > http://www.xilinx.com for all of the details. > > Now I can finally talk about it. Austin, How fast will the MicroBlaze run in the fastest speed grade? Cheers, JonB
Re: Virtex 4 released today - Goran Bilski - 2004-09-14 08:53:00
This is a multi-part message in MIME format. --------------010701070206040609010302 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 8bit Hi, I think it's better that I answer that. MicroBlaze will run about 185 MHz in speedgrade -12. With the new architecture Virtex4, I will need to create a different aspect ratio on the RPM block since this architecture is smaller and higher. VII and V2Pro was more rectangular in the shape. With the new floorplan I achieves 165 MHz in -11 and this will give us around 185 MHz in -12. Göran Bilski Jon Beniston wrote: >Austin Lesea <a...@xilinx.com> wrote in message news:<ci4p3r$i...@cliff.xsj.xilinx.com>... > > >>All, >> >>As Peter would say, the teasing is over: V4 is ALIVE. >> >>http://www.xilinx.com for all of the details. >> >>Now I can finally talk about it. >> >> > >Austin, > >How fast will the MicroBlaze run in the fastest speed grade? > >Cheers, >JonB > > --------------010701070206040609010302 Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN"> <html> <head> <meta http-equiv="Content-Type" content="text/html;charset=ISO-8859-1"> <title></title> </head> <body text="#000000" bgcolor="#ffffff"> Hi,<br> <br> I think it's better that I answer that.<br> MicroBlaze will run about 185 MHz in speedgrade -12.<br> With the new architecture Virtex4, I will need to create a different aspect ratio on the RPM block since this architecture is smaller and higher.<br> VII and V2Pro was more rectangular in the shape.<br> With the new floorplan I achieves 165 MHz in -11 and this will give us around 185 MHz in -12.<br> <br> Göran Bilski<br> <br> Jon Beniston wrote:<br> <blockquote type="cite" cite="m...@posting.google.com"> <pre wrap="">Austin Lesea <a class="moz-txt-link-rfc2396E" href="mailto:a...@xilinx.com"><a...@xilinx.com></a> wrote in message news:<a class="moz-txt-link-rfc2396E" href="mailto:ci4p3r$i...@cliff.xsj.xilinx.com"><ci4p3r$i...@cliff.xsj. xilinx.com></a>... </pre> <blockquote type="cite"> <pre wrap="">All, As Peter would say, the teasing is over: V4 is ALIVE. <a class="moz-txt-link-freetext" href="http://www.xilinx.com">http://www.xilinx.com</a>; for all of the details. Now I can finally talk about it. </pre> </blockquote> <pre wrap=""><!----> Austin, How fast will the MicroBlaze run in the fastest speed grade? Cheers, JonB </pre> </blockquote> </body> </html> --------------010701070206040609010302--______________________________
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Re: Virtex 4 released today - Austin Lesea - 2004-09-14 11:04:00
Jim, Here we go, (below) Austin Jim Granville wrote: > Austin Lesea wrote: > >> Jim, >> >> Thanks for the encouragement, >> >> (long-winded, who me?) > > > You're welcome :) > > To give you a chance to wind up on Virtex-4, here are a > couple of questions : > > Virtex-4 does not seem to be supported in WebPACK > - when is this planned ? Don't know. I am not in the software world at all, so maybe someone else can answer. > > Virtex-4 seems only available in large, BGA packages. Yes, V4 is a flip chip only device due to the ASMBL architecture (no wirebond packages possible). Flip chip does offer real advantages in the SI realm, as the advanced packaging used in V4 has 1/3 to 1/4 the inductance of any other competitive FPGA packaging to date, which will lead to much less ground bounce LdI/dt (SparseChevron-tm power and ground pins are always within 2-3 pins of an IO pin leading to far better SI). Since almost all problems with the most advanced FPGAs have to do with SI (signal integrity engineering on the part of the customer) we decided that we would do what we could to make their job easier. The triple oxide allows us to keep the advantages of the low leakage memory cells for config at 130 nm (and soft error resistance), without any penalty for speed. Using three different oxide thicknesses, and low Vt and high Vt transistors means that an IC designer's choices are much better when it comes to designing for speed, and power. No one else has this triple oxide process, and those that have 100% 90 nm core may have issues with thermal runaway due to leakage, as well as serious power issues. But when customers crank the clock up to 500 MHz, and run all that stuff, even at 40% less dynamic power than V2P, there is 2X the logic per area, so that BGA package is needed to get the heat out! (higher clock rate + more logic in the same space = more heat -- nothing is free). When > do we expect to see Spartan-4? GSD (Spartan) is their own division now, with their own set of customers (set top boxes, big screen TV's, automobiles, etc.) and their needs are quite different. I suspect that Spartan [n+1] devices will look less and less like the APD (Virtex) division devices due to the customer needs. Spartan is all about gates/$ and IO/$. The more, the better. MHz/ns/speed is almost ignored, as long as the devices meet the bare minimum that folks seem to want. There are also issue of low power in these markets, although V4 is 40% less power than V2P for fabric, and 1 mW/100 MHz for the DSP48 MAC blocks (measured on a full FFT from a column of DSP48's), which puts in the best in the world class, as no one is building 90nm DSPs (yet), let alone with kind of performance. The 405PPC core was a low power version for V2P that was redesigned for V4, so it too is extremely low power. I think that V4 is the lowest power part around right now. Spartan plans to catch up, and beat it, however. in TQFP and anything < 360 pins ?. In fact, puting a V4 in a wire bond package (even if it was possible, which it is not) would be like putting a 700 hp V12 in a Austin Mini Cooper: if would fly apart. Sorry, if you want all that performance, it will only come in the package that can handle it. > > Xilinx has a nice Spartan-3 Eval PCB for $99, what is the > Virtex-4 EvalPCB status ? ( $99 ? :) Unknown. Sampling of LX25's is open immediately, with stock. Other parts to follow shortly after I get done verifying and characterizing them (which is pretty easy after we've done the LX25). There is a network board demo'ing 1 GB/s network interfaces, etc with automatic per bit deskew (now built into every IOB). There is a memory interfaces demo board also which shows the superiority of all of the memory interfaces in speed and ease of use. Contact your local FAE or disti. And, there are tons of other boards folks are doing as well, that I do not know about. > > -jg >
Re: Virtex 4 released today - Austin Lesea - 2004-09-14 13:15:00
Antti, The MGT's are designed to address the same standards as V2 Pro and V2 Pro X. That said, the ppm frequency shift of SATA when using spread spectrum clocking (0 to -5000 ppm)is not addressed. Austin Antti Lukats wrote: > "Austin Lesea" <a...@xilinx.com> wrote in message > news:ci4p3r$i...@cliff.xsj.xilinx.com... > >>All, >> >>As Peter would say, the teasing is over: V4 is ALIVE. >> >>http://www.xilinx.com for all of the details. >> >>Now I can finally talk about it. >> >>Austin > > > Any ideas if the V2 rocket MGTs are any better ? > int terms of tolerance to lock freq ppm window and to be able to support > more standards? > > Antti > >
Re: Virtex 4 released today - IgI - 2004-09-14 17:03:00
Hi! A Xilinx representative came today to the company where I work and he had a short but very informative Virtex4 presentation. What I find very useful is that Xilinx finally put a FIFO control logic on BRAMs and significantly increase their performance. Feature to cascade FIFOs will also be very useful for me. I was also hoping to see a 256 deep and 64bit wide BRAMs, but I guess we'll have to wait for that feature for a while? Several times in the past I bumped into the 8 global clocks limitation on Virtex II. That's why I was very exited to hear that I can use up to 32 global clocks, but after reading the Virtex 4 User's guide (page 21) my excitement cooled down a bit. There is a statement: "However, only eight different clocks can be driven in a single clock region. A clock region is a branch of the clock tree consisting of eight CLB rows up and eight CLB rows down. A clock region only spans halfway across the device." If I understand this correctly, there is still a limitation of 8 global clocks per device, that means max. of 8 different and completely unrelated clocks can be used in all regions of the chip? Please, tell me I'm wrong? ;) While further reading documentation, I found there are several new variable phase-shifting modes available. What's got me worried (about my last Virtex-II design) is the following sentence: "Using the variable-positive and variable-center modes the phase can be dynamically and repetitively moved forward and backwards by 1/256 of the clock period.". In my last Virtex-II design I used 2 variable phase shifted clocks and I'm adjusting the phase dynamically all the time. So far the design is working, but can I expect for example that after one million adjustments (for the sake of simplicity let's say each adjustment increases the phase for 100 steps and then decreases the phase for the same amount of steps) the clock phase will still be 0. I know there are many parameters that can have influence on the stability of phase adjusted clock, but have you measured how repetitively accurate is fine phase adjustment in Virtex-II compared to Virtex-4? I believe most of the new features will be very useful, just bring us the productions chips (not ES) as soon as possible, so we won't have to wait too long as it was the case with Virtex-II. I will probably come up with some new questions tomorrow, because I first have to go over the docs/app notes I downloaded today... Regards, Igor Bizjak "Austin Lesea" <a...@xilinx.com> wrote in message news:ci4p3r$i...@cliff.xsj.xilinx.com... > All, > > As Peter would say, the teasing is over: V4 is ALIVE. > > http://www.xilinx.com for all of the details. > > Now I can finally talk about it. > > Austin