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Comp.Arch.FPGA | VHDL gate level from Xilinx XST
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VHDL gate level from Xilinx XST - Laurent Gauch - 2004-09-21 19:10:00
Hi all, I need to generate a part of my VHDL project as a VHDL gate level IP, in the goal to protect my generic IP core. In fact, I want to protect my own PCI core before delivering the complet VHDL project. My question: Is this possible to do a VHDL gate level Netlist from XST. Then to remap it in my VHDL project. Then to do a concatenated VHDL file of by project . Then do a new synthesis and P&R with webpack from my concatenate VHDL file. If yes, how is the best way ? Regards, Larry www.amontec.com______________________________
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