Hello,

I want to compare two designs, one of which is written in verilog
while the other one is in vhdl. the testcases are also written in
verilog. while running the vhdl design, (using XST VHDL) .. the design
compiles without error, but i couldnt figure out a way to generate the
simulation netlist in verilog for the design. does there exist any
such switch using which i can generate a verilog simulation netlist
for designs compiled with XST VHDL

thanks in advance.,

regards
Varun Jindal.

On Tue, 28 Sep 2004 09:21:13 -0700, Varun Jindal
wrote:

> Hello,
> 
> I want to compare two designs, one of which is written in verilog
> while the other one is in vhdl. the testcases are also written in
> verilog. while running the vhdl design, (using XST VHDL) .. the design
> compiles without error, but i couldnt figure out a way to generate the
> simulation netlist in verilog for the design. does there exist any
> such switch using which i can generate a verilog simulation netlist
> for designs compiled with XST VHDL
> 
> thanks in advance.,
> 
> regards
> Varun Jindal.

ngd2ver converts the ngd file to verilog
ngd2vhdl converts the ngd file to VHDL

You don't need to synthesize the designs to simulate them together, any
decent simulator like NCverilog can simulate Verilog and VHDL together.
Take the two sources and put them in the same testbench with some
comparison logic.

Hi

When I am trying to load the verilog design to xst, I am receiving the 
followin errors:

ERROR:HDLParsers:340 Entity <test> does not exist in library <work>
ERROR:Xst:1876 - Entity <test> not found, Recompile it.

I am using the newest Xilinx ISE 6.3i

I have tried to fin out more about this errors on Xilinx web page, but I 
was unsuccessful.

Do you have any ideas how to get rid of this errors??

thank you in advance


Dominik Gawlowski