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Comp.Arch.FPGA | Question for XST expert
There are 3 messages in this thread.
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Question for XST expert - Laurent Gauch - 2004-10-20 07:12:00
Hi all, I am finishing my PCI core. I want to do from XST an .ngc file of my PCI core. The goal is to map IO buffers for all the PCI signal and to let other signals without IO buffer mapping. If I use the XST command line -iobuf , I can only enable or disable the use of IO Buffer on all the port of the entity. Any advice ? Thanks Laurent www.amontec.com
Re: Question for XST expert - Sean Durkin - 2004-10-20 07:47:00
Laurent Gauch wrote on 20.10.2004 13:12: > Hi all, > > I am finishing my PCI core. > > I want to do from XST an .ngc file of my PCI core. > The goal is to map IO buffers for all the PCI signal and to let other > signals without IO buffer mapping. > > If I use the XST command line -iobuf , I can only enable or disable the > use of IO Buffer on all the port of the entity. > > Any advice ? The only way to do this I can think of is to disable automatic IOBUF insertion in XST and manually instantiate IO buffers for those signals you need them for in your VHDL-code. With a few for...generate-statements it shouldn't even be a whole lot of code. cu, Sean
Re: Question for XST expert - Paulo Dutra - 2004-10-20 16:02:00
You could also allow XST to read in the "module" NGC with -read_cores option. Xst will read in your NGC to recognize the logic and infer IO appropriately to the ports that need IO buffers. Sean Durkin wrote: > Laurent Gauch wrote on 20.10.2004 13:12: > >> Hi all, >> >> I am finishing my PCI core. >> >> I want to do from XST an .ngc file of my PCI core. >> The goal is to map IO buffers for all the PCI signal and to let other >> signals without IO buffer mapping. >> >> If I use the XST command line -iobuf , I can only enable or disable >> the use of IO Buffer on all the port of the entity. >> >> Any advice ? > > The only way to do this I can think of is to disable automatic IOBUF > insertion in XST and manually instantiate IO buffers for those signals > you need them for in your VHDL-code. With a few > for...generate-statements it shouldn't even be a whole lot of code. > > cu, > Sean -- / 7\'7 Paulo Dutra (p...@xilinx.com) \ \ ` Xilinx h...@xilinx.com / / 2100 Logic Drive http://www.xilinx.com \_\/.\ San Jose, California 95124-3450 USA