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Comp.Arch.FPGA | Nios & off-chip memory

There are 2 messages in this thread.

You are currently looking at messages 0 to 2.

Nios & off-chip memory - amyler - 2004-10-21 12:29:00

Hi,

I'm using a Nios to access off-chip memories via the SoPC-builer's
external memory bridge. The Nios is 32-bit data, the memories are 
16-bit data. Using SignalTap I can see that Nios is only accessing
even addresses in the external memory (using germs monitor commands
and/or my own c-code). Has anyone there come across something like
this before? Thanks in advance,

Alan Myler



Re: Nios & off-chip memory - George - 2004-10-24 11:13:00

> The Nios is 32-bit data, the memories are 
> 16-bit data. Using SignalTap I can see that Nios is only accessing
> even addresses in the external memory 

Hi Alan:

A classic situation.  The CPU references each byte (8 bits) in memory
using address bit 0.  But the CPU accesses memory in 2 byte chunks (16
bits) so the CPU only needs to output even addresses.  If the program
accesses a byte of data from memory, the CPU reads the 16 bits (even
address) containing that byte and the data bus interface directs
either the high byte or the low byte into the low 8 bits on the CPU
input bus.

If you had a 32 bit wide memory bus the CPU would only read addresses
divisible by 4 and then direct one of the 4 bytes appropiately.

gm