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Comp.Arch.FPGA | PLL Clocks on Cyclone Devices
There are 3 messages in this thread.
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PLL Clocks on Cyclone Devices - Jock - 2004-10-25 09:43:00
Can a Cyclone PLL accept a clipped sine wave with an amplitude of 0.8V - i.e. what is the maximum rise time on the edge of the PLL clock input?______________________________
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Re: PLL Clocks on Cyclone Devices - Rene Tschaggelar - 2004-10-25 15:09:00
Jock wrote: > Can a Cyclone PLL accept a clipped sine wave with an amplitude of 0.8V - > i.e. what is the maximum rise time on the edge of the PLL clock input? What is wrong with a line receiver to meet the AC voltage specifications ? The 1.5V-IO requires 0.35 and 0.65 times 1.5V as levels. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.net______________________________
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Re: PLL Clocks on Cyclone Devices - Jock - 2004-10-26 03:46:00
"Rene Tschaggelar" <n...@none.net> wrote in message news:417d4fca$0$28024$5...@news.sunrise.ch... > Jock wrote: > > > Can a Cyclone PLL accept a clipped sine wave with an amplitude of 0.8V - > > i.e. what is the maximum rise time on the edge of the PLL clock input? > > What is wrong with a line receiver to meet the AC voltage > specifications ? > The 1.5V-IO requires 0.35 and 0.65 times 1.5V as levels. > > Rene > -- > Ing.Buero R.Tschaggelar - http://www.ibrtses.com > & commercial newsgroups - http://www.talkto.net We don't have a lot of real estate and I was looking at ways of reducing component count.