Sign in
Search Comp.Arch.FPGA
fpga by Keywords
Altera | ASIC | CPLD | Cyclone | DCM | DDR | DSP | Ethernet | ISE | JTAG | Linux | LVDS | Microblaze | ML310 | Modelsim | NIOS | OPB | PCI | Quartus | RocketIO | SDRAM | Spartan | Spartan3 | SRAM | Stratix | Verilog | VHDL | Virtex | Virtex-4 | Virtex-II | Xilinx | XST
Ads
See Also
Comp.Arch.FPGA | WebPack - mixed design flow
There are 2 messages in this thread.
You are currently looking at messages 0 to 2.
WebPack - mixed design flow - Valentin Tihomirov - 2003-09-13 09:52:00
My system has netlist in EDIF while some of technology elements used in the netlist are described in a separate VHDL file at logic level. WebPack supports only pure EDIF, schematic, Verilog or VHDL design flows. Is ther a way to compile a mixed design? That is, I first elaborate VHDL and then load EDIF netlist which uses VHDL components. May be ISE Foundation supports this?
Re: WebPack - mixed design flow - Steve Lass - 2003-09-15 13:13:00
ISE version 6.1i supports mixed language flows. ISE Foundation is available now. ISE WebPACK will be ready by the end of this month. Valentin Tihomirov wrote: >My system has netlist in EDIF while some of technology elements used in the >netlist are >described in a separate VHDL file at logic level. WebPack supports only pure >EDIF, schematic, Verilog or VHDL design flows. Is ther a way to compile a >mixed design? >That is, I first elaborate VHDL and then load EDIF netlist which uses VHDL >components. > >May be ISE Foundation supports this? > > > >