1. On a pci target a have on the pci bus signals
pci_ad[31:0] and on
the backend interface a have bkend_data[31:0] (for data r/w) and
backend_adr[31:0] (for address r/w). If I interface a fifo 512x32bits
I must connect bkend_dat[31:0] on the fifoin_dat[31:0]. But fifos
don't have address lines. What shoud I must to do with bkend_ad[31:0]
address lines?? (Put its on high-z ???)
  
   2. If my pci target doesn't meet pci tsu<7ns and tco<11ns it is
posible to work???



 Thanks,

In article
<f...@posting.google.com>,
Dan <d...@gmail.com> wrote:
>I must connect bkend_dat[31:0] on the fifoin_dat[31:0]. But fifos
>don't have address lines. What shoud I must to do with bkend_ad[31:0]
>address lines?? (Put its on high-z ???)

Impossible to say without knowing more about your PCI interface.  However,
if you're using non-addressable memory, what do you expect to do with the
address line?  Does it decode one register that you read repeatedly for
data?  Or does it act like a 'seek' on the fifo?

>   2. If my pci target doesn't meet pci tsu<7ns and tco<11ns it is
>posible to work???

Yes, for experimentation purposes.  Especially if you put the card in the
slot closest to the PCI bridge chip.

-- 
Ben Jackson
<b...@ben.com>
http://www.ben.com/

I must to do some actions that are slowest that
pci_clk and for that I
use a fifo where I store temporary data. I use fifo_full and
fifo_empty signals for make transactions between pci-target and fifo.
I defined that fifo like a memory space with a base_address_register,
and when a have a base_adr_hit for this space I must to write in the
fifo (practicaly I must to write at the same address because fifo has
no address lines).


 Regards,

In article
<f...@posting.google.com>,
Dan <d...@gmail.com> wrote:
>I must to do some actions that are slowest that pci_clk and for that I
>use a fifo where I store temporary data. I use fifo_full and
>fifo_empty signals for make transactions between pci-target and fifo.

So you are using the fifo to buffer for a memory interface that's
not synchronous with the PCI bus?  Then the base address would have
to be stored where you're going to need it to determine where to put
the output side of the fifo.

-- 
Ben Jackson
<b...@ben.com>
http://www.ben.com/