Sign in

username:

password:



Not a member?

Search Comp.Arch.FPGA



Search tips

fpga by Keywords

Altera | ASIC | CPLD | Cyclone | DCM | DDR | DSP | Ethernet | ISE | JTAG | Linux | LVDS | Microblaze | ML310 | Modelsim | NIOS | OPB | PCI | Quartus | RocketIO | SDRAM | Spartan | Spartan3 | SRAM | Stratix | Verilog | VHDL | Virtex | Virtex-4 | Virtex-II | Xilinx | XST

Ads

See Also

DSPEmbedded SystemsElectronics

Comp.Arch.FPGA | DDR Error : partial row address regardless


There are 3 messages in this thread.

You are currently looking at messages 0 to 3.

DDR Error : partial row address regardless - 2004-12-07 23:21:00

Hi,

I use V2P70 to control DDR SDRAM (HY5DU561622CT-J) in the clock of 166MHZ. The row address of this chip if [12:0].

The strange thing is that sometimes one of ddr chip will regardless parital row address[12:9]. Then this chip size is
become from 16Mb * 16 to 1Mb * 16.

What kind of wrong operation will make ddr chip become this error. since the error will recover after power off-on.

BTW, reconfiguation FPGA or reinit DDR SDRAM can not help DDR chip leave from this error.

sincerely, seyor



Re: DDR Error : partial row address regardless - 2004-12-13 01:25:00

HI, I think I have found the problem. The board supports dynamic config FPGA via PCI I/F. Since software set FPGA's
user reset to active before re-config FPGA, the DDR chip will not become error again.

reset it, before re-config it. is this a rule for XILINX? :)

regards, seyior
______________________________
Newest Blog by Chris Felton: "The Spartans". Click here to read.

Re: DDR Error : partial row address regardless - 2004-12-13 01:26:00

HI,

I think I have found the problem. The board supports dynamic config FPGA via PCI I/F. Since software set FPGA's user
reset to active before re-config FPGA, the DDR chip will not become error again.

reset it, before re-config it. is this a rule for XILINX?

regards, seyior