Sign in

username:

password:



Not a member?

Search Comp.Arch.FPGA



Search tips

fpga by Keywords

Altera | ASIC | CPLD | Cyclone | DCM | DDR | DSP | Ethernet | ISE | JTAG | Linux | LVDS | Microblaze | ML310 | Modelsim | NIOS | OPB | PCI | Quartus | RocketIO | SDRAM | Spartan | Spartan3 | SRAM | Stratix | Verilog | VHDL | Virtex | Virtex-4 | Virtex-II | Xilinx | XST

Ads

See Also

DSPEmbedded SystemsElectronics

Comp.Arch.FPGA | cyclone jtag

There are 1 messages in this thread.

You are currently looking at messages 0 to 1.

cyclone jtag - Jedi - 2005-01-18 11:07:00

Has anybody tried to use the
"cyclone_jtag" module in his design?
So I could access registers through JTAG in my design...

I know that I can use opencores jtag module but I want to
use the existing JTAG port.

rick

______________________________
Join the blogging team on FPGARelated.com and earn rewards! Details Here.