Hi,
We are currently using virtexIIpro and virtex4 fpga to prototype a dsp
processor. All the code is synthesizable verilog and we are using
Xilinx ISE to do synthesis and place and route. Everything works fine
and the processor runs at full speed (50Mhz). However, this is only
good for functionnal verification on the bench. The ASIC flow and the
FPGA flow are very different so the actual gates in the FPGA are
different than what will be on the ASIC. For example, we can't use the
FPGA to verify the test vectors and scan chains that the test engineer
is working on.

Is it possible to prototype the EXACT same gates that will be in the
ASIC? We use Synopsys Design Compiler to generate the ASIC gates.
Basically is there a way to take the gates generated by Design
Compiler, and map them in the FPGA? We don't really care if this runs
slower, but it would allow the test engineer to start working on all
the test vectors before we receive silicon.

Thank you very much,
David

On 20 Jan 2005 09:11:59 -0800,
"gretzteam" <d...@gmail.com>
wrote:

>Hi,
>We are currently using virtexIIpro and virtex4 fpga to prototype a dsp
>processor. All the code is synthesizable verilog and we are using
>Xilinx ISE to do synthesis and place and route. Everything works fine
>and the processor runs at full speed (50Mhz). However, this is only
>good for functionnal verification on the bench. The ASIC flow and the
>FPGA flow are very different so the actual gates in the FPGA are
>different than what will be on the ASIC. For example, we can't use the
>FPGA to verify the test vectors and scan chains that the test engineer
>is working on.
>
>Is it possible to prototype the EXACT same gates that will be in the
>ASIC? We use Synopsys Design Compiler to generate the ASIC gates.
>Basically is there a way to take the gates generated by Design
>Compiler, and map them in the FPGA? We don't really care if this runs
>slower, but it would allow the test engineer to start working on all
>the test vectors before we receive silicon.
>
>Thank you very much,
>David

Yes of course. What you need to do is to take the standard cell
library file(s) which define the behavior of individual gates and add
it your gate level netlist during synthesis. All combinational gates
will have their behaviour described in a synthesizable way in the
library. The only case where this will not work are the latches and
flip-flops as they are most probably defined as udps which are not
synthesizable but they are relatively easy to code in behavioral rtl.
the same situation may exists for muxes but that's doable too. but of
course you have to understand that even these gates will be mapped to
the luts on the fpga.

Hi,
thanks for the reply.
Its good news to know that it is possible to do. However, I'm not quite
sure I understand what you are saying. Could you please give more
details of the things to do? Have you ever done it? How good is
performance?

Thanks,
David


mk wrote:
> On 20 Jan 2005 09:11:59 -0800, "gretzteam" <d...@gmail.com>
> wrote:
>
> >Hi,
> >We are currently using virtexIIpro and virtex4 fpga to prototype a
dsp
> >processor. All the code is synthesizable verilog and we are using
> >Xilinx ISE to do synthesis and place and route. Everything works
fine
> >and the processor runs at full speed (50Mhz). However, this is only
> >good for functionnal verification on the bench. The ASIC flow and
the
> >FPGA flow are very different so the actual gates in the FPGA are
> >different than what will be on the ASIC. For example, we can't use
the
> >FPGA to verify the test vectors and scan chains that the test
engineer
> >is working on.
> >
> >Is it possible to prototype the EXACT same gates that will be in the
> >ASIC? We use Synopsys Design Compiler to generate the ASIC gates.
> >Basically is there a way to take the gates generated by Design
> >Compiler, and map them in the FPGA? We don't really care if this
runs
> >slower, but it would allow the test engineer to start working on all
> >the test vectors before we receive silicon.
> >
> >Thank you very much,
> >David
>
> Yes of course. What you need to do is to take the standard cell
> library file(s) which define the behavior of individual gates and add
> it your gate level netlist during synthesis. All combinational gates
> will have their behaviour described in a synthesizable way in the
> library. The only case where this will not work are the latches and
> flip-flops as they are most probably defined as udps which are not
> synthesizable but they are relatively easy to code in behavioral rtl.
> the same situation may exists for muxes but that's doable too. but of
> course you have to understand that even these gates will be mapped to
> the luts on the fpga.

In a similar way to when you use the Xilinx tools
to take a placed and
routed design and produce a VHDL (for example) file which contains a whole
load of simple gates. To simulate this, you either use their library which
includes timing information, or a simple functional description of the
gates. This allows you to test the final design rather than just simulating
the source files.

You should be able to take the output of Design Compiler, and write a simple
functional (and synthesizable) cell library. You could then push all this
through the xilinx tool set and produce a routed design. Of course, the
Xilinx devices use luts as the logic primitive, but you would at least be
starting from the Asic gate description.

/Mike


> Hi,
> thanks for the reply.
> Its good news to know that it is possible to do. However, I'm not quite
> sure I understand what you are saying. Could you please give more
> details of the things to do? Have you ever done it? How good is
> performance?
>
> Thanks,
> David
>
>
> mk wrote:
> > On 20 Jan 2005 09:11:59 -0800, "gretzteam"
<d...@gmail.com>
> > wrote:
> >
> > >Hi,
> > >We are currently using virtexIIpro and virtex4 fpga to prototype a
> dsp
> > >processor. All the code is synthesizable verilog and we are using
> > >Xilinx ISE to do synthesis and place and route. Everything works
> fine
> > >and the processor runs at full speed (50Mhz). However, this is only
> > >good for functionnal verification on the bench. The ASIC flow and
> the
> > >FPGA flow are very different so the actual gates in the FPGA are
> > >different than what will be on the ASIC. For example, we can't use
> the
> > >FPGA to verify the test vectors and scan chains that the test
> engineer
> > >is working on.
> > >
> > >Is it possible to prototype the EXACT same gates that will be in the
> > >ASIC? We use Synopsys Design Compiler to generate the ASIC gates.
> > >Basically is there a way to take the gates generated by Design
> > >Compiler, and map them in the FPGA? We don't really care if this
> runs
> > >slower, but it would allow the test engineer to start working on all
> > >the test vectors before we receive silicon.
> > >
> > >Thank you very much,
> > >David
> >
> > Yes of course. What you need to do is to take the standard cell
> > library file(s) which define the behavior of individual gates and add
> > it your gate level netlist during synthesis. All combinational gates
> > will have their behaviour described in a synthesizable way in the
> > library. The only case where this will not work are the latches and
> > flip-flops as they are most probably defined as udps which are not
> > synthesizable but they are relatively easy to code in behavioral rtl.
> > the same situation may exists for muxes but that's doable too. but of
> > course you have to understand that even these gates will be mapped to
> > the luts on the fpga.
>

If you have a netlist which I am guessing is
mainly ANDs, ORs or even
technology specific elements. You can model each gate/element to an
equivalent in the FPGA. We do this kind of thing for clients from time to
time. More often the biggest issues come in ASIC designs that use a lot of
clocks and have a lot clock boundary crossing. When you get into this type
of design you need to be careful of how it will work in the FPGA. It isn't
impossible but care is needed in designs with large numbers of clocks. As a
side point it is worth looking at Virtex4 for this kind prototyping of as
the family has features aimed at designs with lots of clocks and even clock
boundary crossing assistance.

If at all possible when starting a new design try structure the design to be
friendly to both types of target. If do it early enough is can be a painless
process and does not cost ASIC resource if done properly.

John Adair
Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development
Board.
http://www.enterpoint.co.uk


"gretzteam" <d...@gmail.com> wrote in message
news:1...@z14g2000cwz.googlegroups.com...
> Hi,
> We are currently using virtexIIpro and virtex4 fpga to prototype a dsp
> processor. All the code is synthesizable verilog and we are using
> Xilinx ISE to do synthesis and place and route. Everything works fine
> and the processor runs at full speed (50Mhz). However, this is only
> good for functionnal verification on the bench. The ASIC flow and the
> FPGA flow are very different so the actual gates in the FPGA are
> different than what will be on the ASIC. For example, we can't use the
> FPGA to verify the test vectors and scan chains that the test engineer
> is working on.
>
> Is it possible to prototype the EXACT same gates that will be in the
> ASIC? We use Synopsys Design Compiler to generate the ASIC gates.
> Basically is there a way to take the gates generated by Design
> Compiler, and map them in the FPGA? We don't really care if this runs
> slower, but it would allow the test engineer to start working on all
> the test vectors before we receive silicon.
>
> Thank you very much,
> David
>

OK I understand that you can take the output of
Design Compiler and
feed it through the xilinx tool given I write a library that gives an
FPGA equivalent for each gates. I suppose this would work if the design
is only a bunch of gates with only one clock domain.

Our design has only one clock domain (everything is coded in verilog
with 'enable' line going to every flip flop). However, there is this
step in Design Compiler where you tell it to add 'gated clocks'. As far
as I know, this removes the 'enable' lines and actually clock the flip
flops with divided version of the master clock. It makes sure that the
clock boundaries crossing are ok. How would the xilinx tool handle a
netlist of gates that has all those clock gating circuit?

Thanks,
David


John Adair wrote:
> If you have a netlist which I am guessing is mainly ANDs, ORs or even
> technology specific elements. You can model each gate/element to an
> equivalent in the FPGA. We do this kind of thing for clients from
time to
> time. More often the biggest issues come in ASIC designs that use a
lot of
> clocks and have a lot clock boundary crossing. When you get into this
type
> of design you need to be careful of how it will work in the FPGA. It
isn't
> impossible but care is needed in designs with large numbers of
clocks. As a
> side point it is worth looking at Virtex4 for this kind prototyping
of as
> the family has features aimed at designs with lots of clocks and even
clock
> boundary crossing assistance.
>
> If at all possible when starting a new design try structure the
design to be
> friendly to both types of target. If do it early enough is can be a
painless
> process and does not cost ASIC resource if done properly.
>
> John Adair
> Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3
Development
> Board.
> http://www.enterpoint.co.uk
>
>
> "gretzteam" <d...@gmail.com> wrote in message
> news:1...@z14g2000cwz.googlegroups.com...
> > Hi,
> > We are currently using virtexIIpro and virtex4 fpga to prototype a
dsp
> > processor. All the code is synthesizable verilog and we are using
> > Xilinx ISE to do synthesis and place and route. Everything works
fine
> > and the processor runs at full speed (50Mhz). However, this is only
> > good for functionnal verification on the bench. The ASIC flow and
the
> > FPGA flow are very different so the actual gates in the FPGA are
> > different than what will be on the ASIC. For example, we can't use
the
> > FPGA to verify the test vectors and scan chains that the test
engineer
> > is working on.
> >
> > Is it possible to prototype the EXACT same gates that will be in
the
> > ASIC? We use Synopsys Design Compiler to generate the ASIC gates.
> > Basically is there a way to take the gates generated by Design
> > Compiler, and map them in the FPGA? We don't really care if this
runs
> > slower, but it would allow the test engineer to start working on
all
> > the test vectors before we receive silicon.
> >
> > Thank you very much,
> > David
> >

On 21 Jan 2005 07:56:03 -0800,
"gretzteam" <d...@gmail.com>
wrote:

>OK I understand that you can take the output of Design Compiler and
>feed it through the xilinx tool given I write a library that gives an
>FPGA equivalent for each gates. I suppose this would work if the design
>is only a bunch of gates with only one clock domain.
>
>Our design has only one clock domain (everything is coded in verilog
>with 'enable' line going to every flip flop). However, there is this
>step in Design Compiler where you tell it to add 'gated clocks'. As far
>as I know, this removes the 'enable' lines and actually clock the flip
>flops with divided version of the master clock. It makes sure that the
>clock boundaries crossing are ok. How would the xilinx tool handle a
>netlist of gates that has all those clock gating circuit?
>
Divided clocks are not that difficult but some power optimization
scripts add gated clocks where the clock line is controlled with a
latch and "and" gate sometimes at individual dff level. These would be
more difficult manage. Basically it depends on the number of clock
domains (divided+gated) you're generating.

Sounds like you have a design that would
translate to FPGA easily. There is
some support for gated clocks in more recent Xilinx families but if your
design is only one clock why not simply not let the synthesiser make
sub-clock nets.

For a limited number of clock divisions you could use the DCMs in the FPGA
to do the division. I don't know if your synthesiser could do that
automatically as most don't. If a DCM is used then the Xilinx timing tools
can check automatically that registers in different "related" clock domains
meet setup and hold.

If you generate sub-divisions of clocks using logic then relative phase
timing will vary with every time you build. You can limit the variance by
constraits but still not advised. It is generally far better to use one
clock with clock enables than have splintered clock trees. There may be some
logic size impact although Xilinx FPGA flip-flops have a native, separate,
flip-flop clock enable which has no direct impact on local LUT logic unlike
some competing vendors that share LUT inputs with clock enables.

John Adair
Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development
Board.
http://www.enterpoint.co.uk


"gretzteam" <d...@gmail.com> wrote in message
news:1...@c13g2000cwb.googlegroups.com...
> OK I understand that you can take the output of Design Compiler and
> feed it through the xilinx tool given I write a library that gives an
> FPGA equivalent for each gates. I suppose this would work if the design
> is only a bunch of gates with only one clock domain.
>
> Our design has only one clock domain (everything is coded in verilog
> with 'enable' line going to every flip flop). However, there is this
> step in Design Compiler where you tell it to add 'gated clocks'. As far
> as I know, this removes the 'enable' lines and actually clock the flip
> flops with divided version of the master clock. It makes sure that the
> clock boundaries crossing are ok. How would the xilinx tool handle a
> netlist of gates that has all those clock gating circuit?
>
> Thanks,
> David
>
>
> John Adair wrote:
> > If you have a netlist which I am guessing is mainly ANDs, ORs or even
> > technology specific elements. You can model each gate/element to an
> > equivalent in the FPGA. We do this kind of thing for clients from
> time to
> > time. More often the biggest issues come in ASIC designs that use a
> lot of
> > clocks and have a lot clock boundary crossing. When you get into this
> type
> > of design you need to be careful of how it will work in the FPGA. It
> isn't
> > impossible but care is needed in designs with large numbers of
> clocks. As a
> > side point it is worth looking at Virtex4 for this kind prototyping
> of as
> > the family has features aimed at designs with lots of clocks and even
> clock
> > boundary crossing assistance.
> >
> > If at all possible when starting a new design try structure the
> design to be
> > friendly to both types of target. If do it early enough is can be a
> painless
> > process and does not cost ASIC resource if done properly.
> >
> > John Adair
> > Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3
> Development
> > Board.
> > http://www.enterpoint.co.uk
> >
> >
> > "gretzteam" <d...@gmail.com> wrote in message
> > news:1...@z14g2000cwz.googlegroups.com...
> > > Hi,
> > > We are currently using virtexIIpro and virtex4 fpga to prototype a
> dsp
> > > processor. All the code is synthesizable verilog and we are using
> > > Xilinx ISE to do synthesis and place and route. Everything works
> fine
> > > and the processor runs at full speed (50Mhz). However, this is only
> > > good for functionnal verification on the bench. The ASIC flow and
> the
> > > FPGA flow are very different so the actual gates in the FPGA are
> > > different than what will be on the ASIC. For example, we can't use
> the
> > > FPGA to verify the test vectors and scan chains that the test
> engineer
> > > is working on.
> > >
> > > Is it possible to prototype the EXACT same gates that will be in
> the
> > > ASIC? We use Synopsys Design Compiler to generate the ASIC gates.
> > > Basically is there a way to take the gates generated by Design
> > > Compiler, and map them in the FPGA? We don't really care if this
> runs
> > > slower, but it would allow the test engineer to start working on
> all
> > > the test vectors before we receive silicon.
> > >
> > > Thank you very much,
> > > David
> > >
>