I’m wondering. I wrote the following VHDL-code
(this is only an example, not
something usefull):



library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;



entity counter_test is

    Port ( clk : in std_logic;

           cnt : out std_logic_vector(7 downto 0));

end counter_test;



architecture Behavioral of counter_test is

    signal counter_intern : std_logic_vector (23 downto 0) := (others =>
'0');

begin

    process(clk)

    begin

        if rising_edge(clk) then

            counter_intern <= counter_intern + 1;

        end if;

    end process;

    cnt <= counter_intern(7 downto 0);

end Behavioral;



And when I synthesize it I get the following warnings:



WARNING:Xst:1291 - FF/Latch <counter_intern_22> is unconnected in block
<counter_test>.

WARNING:Xst:1291 - FF/Latch <counter_intern_23> is unconnected in block
<counter_test>.

WARNING:Xst:1291 - FF/Latch <counter_intern_8> is unconnected in block
<counter_test>.

WARNING:Xst:1291 - FF/Latch <counter_intern_9> is unconnected in block
<counter_test>.

WARNING:Xst:1291 - FF/Latch <counter_intern_10> is unconnected in block
<counter_test>.

WARNING:Xst:1291 - FF/Latch <counter_intern_11> is unconnected in block
<counter_test>.

WARNING:Xst:1291 - FF/Latch <counter_intern_12> is unconnected in block
<counter_test>.

WARNING:Xst:1291 - FF/Latch <counter_intern_13> is unconnected in block
<counter_test>.

WARNING:Xst:1291 - FF/Latch <counter_intern_14> is unconnected in block
<counter_test>.

WARNING:Xst:1291 - FF/Latch <counter_intern_15> is unconnected in block
<counter_test>.

WARNING:Xst:1291 - FF/Latch <counter_intern_16> is unconnected in block
<counter_test>.

WARNING:Xst:1291 - FF/Latch <counter_intern_17> is unconnected in block
<counter_test>.

WARNING:Xst:1291 - FF/Latch <counter_intern_18> is unconnected in block
<counter_test>.

WARNING:Xst:1291 - FF/Latch <counter_intern_19> is unconnected in block
<counter_test>.

WARNING:Xst:1291 - FF/Latch <counter_intern_20> is unconnected in block
<counter_test>.

WARNING:Xst:1291 - FF/Latch <counter_intern_21> is unconnected in block
<counter_test>.



Why do I get that when I only want a part of the counter_intern vector?

On Thu, 3 Feb 2005 17:30:40 +0100, "Mr
M" <s...@telia.se> wrote:

>I’m wondering. I wrote the following VHDL-code (this is 
>only an example, not something usefull):

[...]

>use IEEE.STD_LOGIC_ARITH.ALL;
>use IEEE.STD_LOGIC_UNSIGNED.ALL;

Please consider migrating to NUMERIC_STD instead of these
old and poorly-standardised packages.

>entity counter_test is
>    Port ( clk : in std_logic;
>           cnt : out std_logic_vector(7 downto 0));
>end counter_test;

So you have an 8-bit output....

>architecture Behavioral of counter_test is
>    signal counter_intern : std_logic_vector (23 downto 0) 
>                                   := (others => '0');

and a 24-bit internal counter...

>begin
[snip standard counter process]
>
>    cnt <= counter_intern(7 downto 0);

and you port out only the bottom 8 bits of the counter.

>And when I synthesize it I get the following warnings:
>WARNING:Xst:1291 - FF/Latch <counter_intern_22> is unconnected in block

[etc, etc]

>Why do I get that when I only want a part of the counter_intern vector?

Because the synthesis tool has correctly detected that you make no use
of its upper 16 bits, and has optimised them away.  If you had instead
picked the TOP eight bits of the counter...

  cnt <= counter_intern(23 downto 16);

then the tool could not optimise away the lower 16 bits and you
would not get the messages.

Be grateful; the synthesis tool is trying to save you money 
by fitting your design in a smaller part :-)
-- 
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223          mail:j...@doulos.com
Fax: +44 (0)1425 471573                Web: http://www.doulos.com

The contents of this message may contain personal views which 
are not the views of Doulos Ltd., unless specifically stated.

You must admit though that the warning message is
not very clear.Most
compilers at least say something about removing redundant logic.

Thank you :-)



I tried this



library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;



entity counter_test is

    Port ( clk : in std_logic;

           cnt : out std_logic_vector(7 downto 0);

           extra : out std_logic);

end counter_test;



architecture Behavioral of counter_test is

    signal counter_intern : std_logic_vector (23 downto 0) := (others =>
'0');

begin

    process(clk, counter_intern)

    begin

        if rising_edge(clk) then

            counter_intern <= counter_intern + 1;

        end if;

    end process;

    cnt <= counter_intern(8 downto 1);



    extra <= counter_intern(23);

end Behavioral;



I added one more output and copied counter_intern(23) to that output. And
now it works ok.



Now I know why the synthesizer complained.







"Jonathan Bromley" <j...@doulos.com> skrev i meddelandet
news:t...@4ax.com...
> On Thu, 3 Feb 2005 17:30:40 +0100, "Mr M" <s...@telia.se> wrote:
>
> >I'm wondering. I wrote the following VHDL-code (this is
> >only an example, not something usefull):
>
> [...]
>
> >use IEEE.STD_LOGIC_ARITH.ALL;
> >use IEEE.STD_LOGIC_UNSIGNED.ALL;
>
> Please consider migrating to NUMERIC_STD instead of these
> old and poorly-standardised packages.
>
> >entity counter_test is
> >    Port ( clk : in std_logic;
> >           cnt : out std_logic_vector(7 downto 0));
> >end counter_test;
>
> So you have an 8-bit output....
>
> >architecture Behavioral of counter_test is
> >    signal counter_intern : std_logic_vector (23 downto 0)
> >                                   := (others => '0');
>
> and a 24-bit internal counter...
>
> >begin
> [snip standard counter process]
> >
> >    cnt <= counter_intern(7 downto 0);
>
> and you port out only the bottom 8 bits of the counter.
>
> >And when I synthesize it I get the following warnings:
> >WARNING:Xst:1291 - FF/Latch <counter_intern_22> is unconnected in block
>
> [etc, etc]
>
> >Why do I get that when I only want a part of the counter_intern vector?
>
> Because the synthesis tool has correctly detected that you make no use
> of its upper 16 bits, and has optimised them away.  If you had instead
> picked the TOP eight bits of the counter...
>
>   cnt <= counter_intern(23 downto 16);
>
> then the tool could not optimise away the lower 16 bits and you
> would not get the messages.
>
> Be grateful; the synthesis tool is trying to save you money
> by fitting your design in a smaller part :-)
> -- 
> Jonathan Bromley, Consultant
>
> DOULOS - Developing Design Know-how
> VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services
>
> Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
> Tel: +44 (0)1425 471223          mail:j...@doulos.com
> Fax: +44 (0)1425 471573                Web: http://www.doulos.com
>
> The contents of this message may contain personal views which
> are not the views of Doulos Ltd., unless specifically stated.
>