Hi !

Thanks for the great help offered by the group to our FPGA issues.
This time the queries are:

1) I am planning to use a LM317(National Semi) Regulator to power my
board having Spartan2 XC2S150 and some other TTL Ics. Would this
regulator be able to provide the required POS current [power on surge
current] for the FPGA? What current rating is recommended? 2A or more?
If this is not good, which regulator would be OK?

2)I have a 20MHz clock in my design that is used in some flip flops in
the design. Most of the circuit is combinational and with about 18
combinational clocks. What bypass capacitor ratings would be OK for my
design .01uf would be OK?

3)In XST 5.1i , there is a synthesis option which says "Add I/O
buffers". Does that mean that if i check this option, the XST would
automatically insert I/O buffers[IBUF,OBUF,IBUFG,OBUFT etc] into my
top-level module ports and i don't have to instantiate these I/O
buffers into my HDL code?

Thanks
Rider

s...@yahoo.com (rider) wrote in message
news:<c...@posting.google.com>...
> Hi !
> 
> Thanks for the great help offered by the group to our FPGA issues.
> This time the queries are:
> 
> 1) I am planning to use a LM317(National Semi) Regulator to power my
> board having Spartan2 XC2S150 and some other TTL Ics. Would this
> regulator be able to provide the required POS current [power on surge
> current] for the FPGA? What current rating is recommended? 2A or more?
> If this is not good, which regulator would be OK?

LM317 is fine, but is kind old style
the rating depends on the voltage drop on regulator
if the incoming voltage is low then you can use some
nice regulators in SOT223 package they are sufficient
(but will get a little hot/warm)
with LDO regulators check the special required bypass caps!
 
> 2)I have a 20MHz clock in my design that is used in some flip flops in
> the design. Most of the circuit is combinational and with about 18
> combinational clocks. What bypass capacitor ratings would be OK for my
> design .01uf would be OK?

I use always 0.1 there is not much difference in size or prics
its 0603 package always
 
> 3)In XST 5.1i , there is a synthesis option which says "Add I/O
> buffers". Does that mean that if i check this option, the XST would
> automatically insert I/O buffers[IBUF,OBUF,IBUFG,OBUFT etc] into my
> top-level module ports and i don't have to instantiate these I/O
> buffers into my HDL code?

correct.

antti

1)  the LM317 meet sthe datasheet requirements
(current and current
limiting)

2) use 0.1uF caps.  surface mount 0402, or 0406.  One each for every power
and ground pin pair.  X7R material.  Keep inductance down to min.  Read th
SI Central web pages on power distribution systems.

20MHz is not the issue, it is the edge rates.

Austin

rider wrote:

> Hi !
>
> Thanks for the great help offered by the group to our FPGA issues.
> This time the queries are:
>
> 1) I am planning to use a LM317(National Semi) Regulator to power my
> board having Spartan2 XC2S150 and some other TTL Ics. Would this
> regulator be able to provide the required POS current [power on surge
> current] for the FPGA? What current rating is recommended? 2A or more?
> If this is not good, which regulator would be OK?
>
> 2)I have a 20MHz clock in my design that is used in some flip flops in
> the design. Most of the circuit is combinational and with about 18
> combinational clocks. What bypass capacitor ratings would be OK for my
> design .01uf would be OK?
>
> 3)In XST 5.1i , there is a synthesis option which says "Add I/O
> buffers". Does that mean that if i check this option, the XST would
> automatically insert I/O buffers[IBUF,OBUF,IBUFG,OBUFT etc] into my
> top-level module ports and i don't have to instantiate these I/O
> buffers into my HDL code?
>
> Thanks
> Rider

rider wrote:

> 2)I have a 20MHz clock in my design that is used in some flip flops in
> the design. Most of the circuit is combinational and with about 18
> combinational clocks. 
That is a scary statement.
Are you really using 18 clocks driven by combinatorial logic?
You must be either very inexperienced, very brave, or very smart. Or
perhaps all three.
Normal humans stay away from such design methodologies, and use
synchronous logic with a minimum of global clocks (preferrably only one).
That's better for your health, your sleep, and your sanity...
Peter Alfke

Peter Alfke wrote:

>rider wrote:
>
>  
>
>>2)I have a 20MHz clock in my design that is used in some flip flops in
>>the design. Most of the circuit is combinational and with about 18
>>combinational clocks. 
>>    
>>
>That is a scary statement.
>Are you really using 18 clocks driven by combinatorial logic?
>You must be either very inexperienced, very brave, or very smart. Or
>perhaps all three.
>Normal humans stay away from such design methodologies, and use
>synchronous logic with a minimum of global clocks (preferrably only one).
>That's better for your health, your sleep, and your sanity...
>Peter Alfke
>  
>
Well, he's certainly using the right (read ONLY) architecture that will 
do it.
I got started with Xilinx on a project where I needed 72 flip-flops on a
board, all essentially asynchronous from any other.  (This was a timing and
logic controller for nuclear detector applications).  Xilinx was the ONLY
architecture that could handle lots of acynchronous clocks at the time.  It
may still be.  There certainly can be complications with things like this.

We needed to have totally asynchronous timing, with resolution below 1
nS, so no global clock could do it.  We used the AD9201 timing chip to 
handle
the time delays, but that chip lacks a FF to make it into a one-shot 
function,
which was what we needed.

Jon

Jon, I was making a general statement in favor of
synchronous design.
Smart people using smart hardware can violate all these "rules"...
I am glad Xilinx ( the ONLY one) worked out for you.  :-)

Peter Alfke
=============================
Jon Elson wrote:
> 
> P
> >
> >
> Well, he's certainly using the right (read ONLY) architecture that will
> do it.
> I got started with Xilinx on a project where I needed 72 flip-flops on a
> board, all essentially asynchronous from any other.  (This was a timing and
> logic controller for nuclear detector applications).  Xilinx was the ONLY
> architecture that could handle lots of acynchronous clocks at the time.  It
> may still be.  There certainly can be complications with things like this.
> 
> We needed to have totally asynchronous timing, with resolution below 1
> nS, so no global clock could do it.  We used the AD9201 timing chip to
> handle
> the time delays, but that chip lacks a FF to make it into a one-shot
> function,
> which was what we needed.
> 
> Jon

Peter Alfke <p...@xilinx.com> wrote in
message news:<3...@xilinx.com>...
> rider wrote:
> 
> > 2)I have a 20MHz clock in my design that is used in some flip flops in
> > the design. Most of the circuit is combinational and with about 18
> > combinational clocks. 
> That is a scary statement.
> Are you really using 18 clocks driven by combinatorial logic?
> You must be either very inexperienced, very brave, or very smart. Or
> perhaps all three.
> Normal humans stay away from such design methodologies, and use
> synchronous logic with a minimum of global clocks (preferrably only one).
> That's better for your health, your sleep, and your sanity...
> Peter Alfke

Peter!

Thanks for pointing out the issue. You are right about the synchronous
clock issue. I know its not good to use asynchronous designs, but i
have a different problem at hand. I am actually doing reverse
engineering of a board made in probably 1980. It has more than 200
I/Os and over 180 TTL ICs. I have a rough schematic of it and no other
info. So, I thought it wouldn't be practical to start tracing the
boards functionality and make it SYNCHRONOUS ...and it may never be
possible i feel...so i had to go with combinatorial clocks which the
design is already using..

Now i know synchronous design has its advantages, but does that mean
that asynchronous design will never work..in discrete ICs or in FPGA?
Please comment..

Rider

rider wrote:

> I/Os and over 180 TTL ICs. I have a rough schematic of it and no other
> info. So, I thought it wouldn't be practical to start tracing the
> boards functionality and make it SYNCHRONOUS ...and it may never be
> possible i feel...so i had to go with combinatorial clocks which the
> design is already using..

Make sure there are no reports of "flakiness"
with the old design.

But say we assume that the TTL designers got it right,
and that all of the logic races were skewed in the
right direction for reliable operation.

Now you change from TTL to cmos/FPGA
and a new set of races are on.
I expect that the time you save by skipping
a redesign will be more that used up
by debugging logic races.

> Now i know synchronous design has its advantages, but does that mean
> that asynchronous design will never work..in discrete ICs or in FPGA?

An asynchronous design can work, but it is *very* difficult to prove
that that it will always work over time and environment.
Even the simplest case of building a reliable d-flop primitive
is non-trivial.

It a simple task to prove reliablility on a synchronous design.

  -- Mike Treseler

I remember the 70's well.  :-)
The TTL logic we used was slow by today's standards, with output delays
of 25 ns and gentle rise and fall times.
But the interconnect was fast, just wires, at 1 to 2 ns per foot.

Now, in FPGAs, you have very fast logic, with extremely short transition
times of <1ns, but the FPGA-internal interconnects are comparatively
slow. It is now fairly normal to spend as much time travelling in the
on-chip interconnects, as propagating through the logic.  In the old
TTL/MSI days, the logic and the flip-flops were very much slower than
the interconnect.

That means: The slow logic used to tolerate and swallow up interconnect
delays, and the transitions were so slow that there were hardly any
transmission-line effects.
Now the logic is so fast and unforgiving, that the interconnect delays
can no longer be ignored, and almost any pc-board trace must be treated
as a transmission line.

These "cultural differences" may bite you in your translation effort.
So, beware of decoding glitches on the clock lines, of uncontrolled
clock distribution delay differences, and hold time issues. And crank
the chip-output drivers down to the weakest drive strength!
You do not need speed; speed is your enemy, but the enemy is very much alive...

Have fun!
Peter Alfke
==========================
rider wrote:
> 
>. You are right about the synchronous
> clock issue. I know its not good to use asynchronous designs, but i
> have a different problem at hand. I am actually doing reverse
> engineering of a board made in probably 1980. It has more than 200
> I/Os and over 180 TTL ICs. I have a rough schematic of it and no other
> info. So, I thought it wouldn't be practical to start tracing the
> boards functionality and make it SYNCHRONOUS ...and it may never be
> possible i feel...so i had to go with combinatorial clocks which the
> design is already using..
> 
> Now i know synchronous design has its advantages, but does that mean
> that asynchronous design will never work..in discrete ICs or in FPGA?
> Please comment..
> 
> Rider

Hi Rider,
      As others have said, you'll probably find 2) quite tricky. Why
not synchronously clock the whole thing a lot faster, say 100MHz, and
make synchronous models of the slow logic and FFs? This way you
overcome the hideous skew problems? The old TTL switches slowly so any
10ns latency due to the 100MHz clock won't matter. Modern FPGAs have
many orders of magnitude more logic than TTL so the extra gates aren't
a problem.
      Just an idea, Syms.


s...@yahoo.com (rider) wrote in message
news:<c...@posting.google.com>...
> Hi !
> 
> Thanks for the great help offered by the group to our FPGA issues.
> This time the queries are:
> 
> 1) I am planning to use a LM317(National Semi) Regulator to power my
> board having Spartan2 XC2S150 and some other TTL Ics. Would this
> regulator be able to provide the required POS current [power on surge
> current] for the FPGA? What current rating is recommended? 2A or more?
> If this is not good, which regulator would be OK?
> 
> 2)I have a 20MHz clock in my design that is used in some flip flops in
> the design. Most of the circuit is combinational and with about 18
> combinational clocks. What bypass capacitor ratings would be OK for my
> design .01uf would be OK?
> 
> 3)In XST 5.1i , there is a synthesis option which says "Add I/O
> buffers". Does that mean that if i check this option, the XST would
> automatically insert I/O buffers[IBUF,OBUF,IBUFG,OBUFT etc] into my
> top-level module ports and i don't have to instantiate these I/O
> buffers into my HDL code?
> 
> Thanks
> Rider