Peter Alfke <p...@xilinx.com> wrote in
message news:<3...@xilinx.com>...
> I remember the 70's well.  :-)
> The TTL logic we used was slow by today's standards, with output delays
> of 25 ns and gentle rise and fall times.
> But the interconnect was fast, just wires, at 1 to 2 ns per foot.
> 
> Now, in FPGAs, you have very fast logic, with extremely short transition
> times of <1ns, but the FPGA-internal interconnects are comparatively
> slow. It is now fairly normal to spend as much time travelling in the
> on-chip interconnects, as propagating through the logic.  In the old
> TTL/MSI days, the logic and the flip-flops were very much slower than
> the interconnect.
> 
> That means: The slow logic used to tolerate and swallow up interconnect
> delays, and the transitions were so slow that there were hardly any
> transmission-line effects.
> Now the logic is so fast and unforgiving, that the interconnect delays
> can no longer be ignored, and almost any pc-board trace must be treated
> as a transmission line.
> 
> These "cultural differences" may bite you in your translation effort.
> So, beware of decoding glitches on the clock lines, of uncontrolled
> clock distribution delay differences, and hold time issues. And crank
> the chip-output drivers down to the weakest drive strength!
> You do not need speed; speed is your enemy, but the enemy is very much alive...
> 
> Have fun!
> Peter Alfke
> ==========================

Hi All!

Thanks for everyone for comments on my design. All those comments are
scaring me . So please help me out in this situation. I try to explain
the design a bit.

As i told, the design has around 200+ IO's with more than 80 inputs
and nearly 180 ICs. No information on these inputs is avaialble apart
from their connections, from the schematic. There are around 24 Flip
flops (D and JK type) and few other ICs requiring clocks. We have an
on board clock of 20Mhz which is clocking some of FFs, while some are
clocked from external port inputs and some from Combinatorial clocks.
The design is clearly Asynchronous. Also due to non-avaialability of
information about IOs, i cant trace the design functionality(due to
massive nets). What i have done is modeled the possible ICS in Verilog
and instantiated them as per schematic. the few observations are:

1)Some FFs have their inputs permanently tied to 1 or 0. (OK i feel?)

2)Some FFs share common clock but their inputs are combinational logic
comprised of other FFs(same clock). (Its OK i guess).

3)Here seems a problem: A FF is clocked by local 20MHz clock, but its
input is a combinational logic which itself derives it inputs from
outputs of FFs clocked by signals from 2 external ports. (Clearly
Asynchronous. So why did the designer use it? How could he have been
sure at that time that their is no asynchronous effect?)

4)An input from IO port passes through a buffer IC . This buffer's
output makes input to a clocked IC, which is inturn clocked by a
combinatorial logic. Again asynchronous.

The card is authentic and from a reliable company. My question is that
wasn't there any concern at that time(1980) of asynchronous design
that the designer has used so much asynchronous techniques? Is it
possible that there is no such REQUIREMENT of synchronism in this
design(the system interfacing to IOs of card can handle it ? of which
we have no knowledge). Isn't asynchronous design a necessasity times
when either synchronous design is neither possible nor feasible?
Also why i am gonna be in trouble? Because i am shifting to FPGA OR
theere would be same problems even if i redesign the card with same
components it is now using? If FPGA is a problem, then why do they
claim that we can translate our obselete components into FPGA? If a
design is asynchronous inherently, should we forcibly synchronise it
mere for the sake of FPGA implemenatation?

Thanks to all who commented.

Rider

Only 24 FFs?

Sounds like the board synchronizes incoming data+clock to one system
clock. Maybe there is som metastability improvmenet technique
incorporated.

Do the FF IC:s have clock enable? If not, that could be done by using
combinatorial clocks.

Is there much feedback between all the FF:s? If so, I guess there is
some state machine in there (scary...), if not then I'm sure it's
relatively easy to reverse engineer the board.

What's the board'sfunction, anyway? That would give you a good start.

Homann
-- 
Magnus Homann, M.Sc. CS & E
d...@dtek.chalmers.se

>The card is authentic and from a reliable
company. My question is that
>wasn't there any concern at that time(1980) of asynchronous design
>that the designer has used so much asynchronous techniques?

Do you have the schematics?  If so, look for the standard
clock-qualifier pattern.  The clock will run into one side of
an '00 and the qualifying signal will run into the other side.
The output is a qualified clock.  It will look like an asynchronous
clock to the FPGA tools, but it really was synchronous in the
designer's mind.

This was used because chips like a '374 didn't have a clock
qualifing input pin.

A common clock distribution scheme in the old TTL days was
that the master clock from the osc clocked a FF to square things
up and the output of the FF then fanned out to several buffers
and they went to another layer of '00s which were buffers
and qualifiers.  Allways running clocks went through a
dummy '00 to balance the skew (and get the polarity right).

You could also get similar qualified clocks out of a '138 or '139
by feeding the clock into the enable pin.  This gets you 1 of N
decoding for things like writing to 1 of several chips.  The skew
wasn't as well balanced but it generally worked well enough.

Note that all of the '00s used in the clock distribution chain
were the same technology - no mixing LS and F as that would mess
up the clock skew.

-- 
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Hi Jon,

> Well, he's certainly using the right (read ONLY) architecture that will
> do it.
> I got started with Xilinx on a project where I needed 72 flip-flops on a
> board, all essentially asynchronous from any other.  (This was a timing
and
> logic controller for nuclear detector applications).  Xilinx was the ONLY
> architecture that could handle lots of acynchronous clocks at the time.
It
> may still be.  There certainly can be complications with things like this.

I'm curious -- why do you believe that "ONLY" Xilinx architectures will work
for "asynchronous" clocks?  I know the Stratix/Cyclone families of Altera
very well, and cannot see why they cannot handle such designs.  I am also
hard-pressed to figure out where the defficiency is in APEX/FLEX too, though
I am less familiar with them.

One thing I'd like to point out is that Stratix (when I compare to
Virtex-II) has significantly more global clocking available.  There are 16
global clocks (8 to each quadrant) in Virtex II, while Stratix has 16 truely
global clocks, plus 16 quadrant clocks (4 per quadrant) and 2
quadrant/octant fast clocks.  In a 1S80 device, this means there are a total
of 48 independent clocks available to you.  What does this mean?  You're
less likely to have to rely on locally routed clocks or other such things
that make getting a design right that much harder.

Regards,

Paul Leventis
Altera Corp.

Paul,

You forgot that we also have dedicated clocks to deal with the clock
domains from high-speed IOs, which are localized around the IOs and
the dedicated serialization / deserialization hardware we have for
high-speed LVDS.  There are 16 extra dedicated clocking resources
around the IOs for this, giving a total of 64 independent clocks on
dedicated resources in a 1S80.

Vaughn



"Paul Leventis" <p...@utoronto.ca> wrote in message
news:<oR6eb.162258$L...@news01.bloor.is.net.cable.rogers.com>...
> Hi Jon,
> 
> I'm curious -- why do you believe that "ONLY" Xilinx architectures will
work
> for "asynchronous" clocks?  I know the Stratix/Cyclone families of Altera
> very well, and cannot see why they cannot handle such designs.  I am also
> hard-pressed to figure out where the defficiency is in APEX/FLEX too, though
> I am less familiar with them.
> 
> One thing I'd like to point out is that Stratix (when I compare to
> Virtex-II) has significantly more global clocking available.  There are 16
> global clocks (8 to each quadrant) in Virtex II, while Stratix has 16 truely
> global clocks, plus 16 quadrant clocks (4 per quadrant) and 2
> quadrant/octant fast clocks.  In a 1S80 device, this means there are a total
> of 48 independent clocks available to you.  What does this mean?  You're
> less likely to have to rely on locally routed clocks or other such things
> that make getting a design right that much harder.
> 
> Regards,
> 
> Paul Leventis
> Altera Corp.