hi all

I am wondering if it is feasible for OPB to connect microblaze and
BRAMS.

For instance, OPB connects one microblaze and 2 64KB BRAMS (with
different address map). Each BRAM is instruction/data dual port. So
programmer may consider the system has 128 KB memory space.

How do you find this scheme? Are there any other things to consider?

thankyou for reply

Hi,

You can have as many BRAM memory blocks (up to the limit of your FPGA) on LMB 
and OPB.

One the LMB, just create two bram blocks and four lmb bram controllers and two 
lmb busses.

One the OPB, you can either have one OPB bus with two opb bram controller. This 
is a now a shared bus between instruction and data side of MicroBlaze.
IF you want more speed you can create two OPB busses and do the same as for the LMB.

All this is very easy to do in the XPS tool.

I would go for the LMB since it has lower latency for memory access than the OPB.

Göran

Jack wrote:
> hi all
> 
> I am wondering if it is feasible for OPB to connect microblaze and
> BRAMS.
> 
> For instance, OPB connects one microblaze and 2 64KB BRAMS (with
> different address map). Each BRAM is instruction/data dual port. So
> programmer may consider the system has 128 KB memory space.
> 
> How do you find this scheme? Are there any other things to consider?
> 
> thankyou for reply
>