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Comp.Arch.FPGA | RocketIO minimum bitrate and other questions

There are 2 messages in this thread.

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RocketIO minimum bitrate and other questions - Wing Fong Wong - 2005-03-01 23:27:00

I know this may seem like a strange question but
what is the minimum 
bitrate that data can be sent through the RocketIO port?

Just another question while I'm here, anyone Xilinx people out there 
really familiar with the Xilinx ML310 board with the Virtex-II pro fpga? 
I just want to know what is the best way to interface 50 odd digital I/O 
lines to it. About half of the lines will be input and the other half will 
be output.

-- 

Wing Wong.
Webpage: http://wing.ucc.asn.au
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Re: RocketIO minimum bitrate and other questions - Jonathan Swift - 2005-03-02 08:43:00

Wing Fong Wong wrote:

>I know this may seem like a strange question but what is the minimum 
>bitrate that data can be sent through the RocketIO port?
>
>Just another question while I'm here, anyone Xilinx people out there 
>really familiar with the Xilinx ML310 board with the Virtex-II pro fpga? 
>I just want to know what is the best way to interface 50 odd digital I/O 
>lines to it. About half of the lines will be input and the other half will 
>be output.
>
>  
>
Just using the RocketIO the lowest bitrate is 600Mbps in the Virtex-II 
Pro. However you can implement an oversampling technique in the logic 
fabric which allows you go slower, see XAPP572 for more details on the 
technique we've used for data rates down to 200Mbps. Using the same 
principles but with greater oversampling 155Mbps is possible with good 
results.

Jonathan