Hello, I've been hearing a lot about DSP Builder
and was curious if it
is worth learning? Can anyone share their experience pros/cons? Are
they any good references I could pick and teach myself?

Thanks,
joe

I have used it during some month for a trainee
and it is really easy too 
use, if you already use simulink , it is the same thing. You could use all 
matlab functions to generate your stimuli and analyze result. But I think 
it's mainly powerfull for signal processing application not for making state 
machine or thing like that.
For reference look at simulink ref , if you know well matlab/simulink well 
you are ready to use dsp builder.

The way we used it during my internship was to make some part of the design 
with DSP Builder then generate the netlist (i'm not sure that really a 
netlist it's a *.vqm file) and integrated to the the final project in 
quartus

I ask my self if there is not already an other tool non-dependant of a FPGA 
firm that t just convert a simulink file to vhdl or verilog, it probably 
need some specific library but it should be too hard to implement such tool.

alexis


<j...@hotmail.com> a écrit dans le message de news: 
1...@z14g2000cwz.googlegroups.com...
> Hello, I've been hearing a lot about DSP Builder and was curious if it
> is worth learning? Can anyone share their experience pros/cons? Are
> they any good references I could pick and teach myself?
>
> Thanks,
> joe
> 

j...@hotmail.com wrote:
> Hello, I've been hearing a lot about DSP Builder and was curious if
it
> is worth learning?

Where have you been hearing about it ?

> Can anyone share their experience pros/cons? Are

I did one commercial design with DSP Builder about a year ago.  I can
conceive that for a suitable complex design DSPBuilder would permit
realization considerably faster than doing the design directly in VHDL.
 But I found it to be buggy and limited in _many_ different ways, and
the overhead of finding, understanding and working around DSPBuilder's
limitations was a HUGE burden that I would not wish on anyone.  The
second design will go much more smoothly than the first -- if you
should live so long.  I did finish my project, however it is maintained
in VHDL; the Simulink model is not close enough to the final
implementation to be worth keeping around, except for the approximate
graphical view of the design.

Perhaps there have been substantial improvements in recent releases.
Perhaps learning Xilinx' SystemGenerator is a better bet.

> they any good references I could pick and teach myself?
> 
> Thanks,
> joe

Regards,
-rajeev-