I try to access the SDRAM in my program, and wait
for enough time before writing data to SDRAM,but i find the value of SDRAM is FF,what
should i do ? what is wrong?

"ARRON" <m...@gmail.com>
schrieb im Newsbeitrag
news:ee8e5aa.-1...@webx.sUN8CHnE...
> I try to access the SDRAM in my program, and wait for enough time before
writing data to SDRAM,but i find the value of SDRAM is FF,what should i do ?
what is wrong?

give more info in first place!
what board
what device
what sdram controller IP core
how its wired
etc..

there could zilions of problems.

the readout FF itself means nothing and is not enough to give you an answer

Antti

my FPGA board is XILINX VIRTEX II pro of Memec
Design, and the sdram controller IP core is OPB_SDRAM, I add the IP core when i generate a
project at the BSB, I think it's wires are not wrong, BUT i don't know the flow of
accessing SDRAM, can you help me ?

ARRON wrote:
> my FPGA board is XILINX VIRTEX II pro of Memec Design, and the sdram
controller IP core is OPB_SDRAM, I add the IP core when i generate a
project at the BSB, I think it's wires are not wrong, BUT i don't know
the flow of accessing SDRAM, can you help me ?

You might want to read the fine data sheets for the SDRAM devices.
Hint: Micron and Samsung have excellent data sheets.

-a

I have tested my project,but i find writing the
SDRAM will success if the system's cpu is ppc,when the cpu is Microblaze,that i write to
the SDRAM must wait for initializing the SDRAM and will not success, what is the matter?
which parameter of SDRAM controller must be changed? thanks for your help!!!

ARRON wrote:
> I have tested my project,but i find writing the SDRAM will success if
the system's cpu is ppc,when the cpu is Microblaze,that i write to the
SDRAM must wait for initializing the SDRAM and will not success, what
is the matter? which parameter of SDRAM controller must be changed?
thanks for your help!!!

Without looking at your design (and no, I don't want to see it), I'd
wager that the interface between the processor and the SDRAM controller
has to change when you change the processor.  Different timing and
different bus transactions, perhaps?

-a

Hi,ARRON, I am afraid in current releases of EDK
tools, there is a bug for SDRAM IP. In EDK,open the system.ucf file, to see if the
Bank_Addr[] io pins are included in the ucf,if not,then you should manually add these
clauses to the ucf. Good luck. jeffsen

hello,jeffsen and everyone, i have compared the
ucf file of ppc project with MICROBLAZE.I don't find the omitted pin, so i think i should
modify the parameter of opb_sdram_controller in MICROBLAZE project(IN PPC project is
PLB_SDRAM_CONTROLLER),i will try it,thanks your help!!!

Today i have tried to modify the parameters:
CAS_LAT from 2 to 3,TREF from 64 to 32,and find this have nothing effect in the programm.
Now i can assure the problem of reading or writing SDRAM has relation with the cpu. In the
Powerpc, the operationt is all right,but in the Microblaze, the Wrong is inevitable, i
need more advice, i need your help!