Sign in

username:

password:



Not a member?

Search Comp.Arch.FPGA



Search tips

fpga by Keywords

Altera | ASIC | CPLD | Cyclone | DCM | DDR | DSP | Ethernet | ISE | JTAG | Linux | LVDS | Microblaze | ML310 | Modelsim | NIOS | OPB | PCI | Quartus | RocketIO | SDRAM | Spartan | Spartan3 | SRAM | Stratix | Verilog | VHDL | Virtex | Virtex-4 | Virtex-II | Xilinx | XST

Ads

See Also

DSPEmbedded SystemsElectronics

Comp.Arch.FPGA | ALTERA EPXA1 SDRAM BUG

There are 1 messages in this thread.

You are currently looking at messages 0 to 1.

ALTERA EPXA1 SDRAM BUG - Ralf - 2005-05-20 06:57:00

Hi all,

have everyone experience about a second SDRAM with the Altera
FPGA+HARCORE-CPU EPXA1?
Its is unpossible for me to access the second SDRAM.
I used a modified "Hello World" program from ALTERA, Linux running on the
hardcore CPU and ARMBOOT to address the second SDRAM (Chip-Select SD-CS1)
device. But I always get the content of the first SDRAM (Chip-Select
SD-CS0). Both SDRAM devices shared the address and data signals, but every
device get his own chip_select signal.

I would appreciate any help in solving this problem.

Regards Ralf


______________________________
Join the blogging team on FPGARelated.com and earn rewards! Details Here.