Sign in

username:

password:



Not a member?

Search Comp.Arch.FPGA



Search tips

fpga by Keywords

Altera | ASIC | CPLD | Cyclone | DCM | DDR | DSP | Ethernet | ISE | JTAG | Linux | LVDS | Microblaze | ML310 | Modelsim | NIOS | OPB | PCI | Quartus | RocketIO | SDRAM | Spartan | Spartan3 | SRAM | Stratix | Verilog | VHDL | Virtex | Virtex-4 | Virtex-II | Xilinx | XST


Ads

See Also

DSPEmbedded SystemsElectronics

Comp.Arch.FPGA | Xilinx Virtex 4 Configuration Frames

There are 1 messages in this thread.

You are currently looking at messages 0 to 1.

Xilinx Virtex 4 Configuration Frames - lovesinghal@gmail.com - 2005-05-24 04:06:00

Hello All,

I am looking at the reconfiguration capabilities of Virtex 4 devices. I
have following questions related to Xilinx Virtex 4 configuration
frames (frames here refer to the smallest addressable units in Virtex
devices that can be reconfigured):

a). What is the shape and size of a frame in Virtex 4 device? I know
that in Virtex 2, each frame is one vertical column of the device. I
also know that in Virtex 4 each frame contains fixed 41 words of data.
But I could not find any information related to its shape in Virtex 4.

b). How many CLBs does one frame include or vice versa?

c). I have seen somewhere that Virtex 4 is a tile based device. Does it
mean that each configuration frame is completely contained in one tile?
If yes, how many frames/CLBs does one tile contain?

d). Can we use the Xilinx JBits SDK to configure a Virtex 4 frame? The
documentation for JBits 3.0 does not refer to Virtex 4 and only seems
to support Virtex 2. If it doesn't support Virtex 4, what is the
equivalent toolkit for Virtex 4 devices?

Thanks in advance,
Love Singhal