Hello,

I've an Virtex II (later it'll be a Spartan 3) witch is connected to
external asynchronous SRAM. Now I would like to access it in the same
way as a synchronous SRAM (like a BRAM for example). I think reading
should work in the same way as with an synchronous SRAM (set address
and /oe and read data at the next clock) as long the SRAM is fast
enough. But I've no idea how to implement a write access in an
efficient way. I could set address, data and /wr and create some logic
that clears the /wr signal at the falling edge of the clocksignal. But
so I could only use half the speed of the SRAM because the /wr signal
would only high for half the clock period.
Please let me know if there is any better way to implement this.

Michael

"Michael Dreschmann"
<m...@gmx.de> wrote
> ... external asynchronous SRAM. ...
> But I've no idea how to implement a write access in an
> efficient way.

Search for discussions of this in the past (fpga-faq.com).  Also, here's how 
I did this long ago -- too clever by half, I'm afraid: 
http://groups.yahoo.com/group/fpga-cpu/message/539.

Jan Gray

Ok, Thnx

Michael

Michael,

 Another thread on the fpga-cpu group discussed creating
such a gated write strobe by using the DDR output registers
found in S3 & V2:

 http://groups.yahoo.com/group/fpga-cpu/message/2076

I also posted a first pass at a memory test using this
technique for the Xilinx S3 starter kit here:

 http://groups.yahoo.com/group/fpga-cpu/message/2177

Brian