what about this error?

--------------------------------- INTERNAL_ERROR:Xst:cmain.c:3022:1.146.4.1 - To resolve
this error, please consult the Answers Database and other online resources at
<http://support.xilinx.com>; ERROR: XST failed Process "Synthesize" did not
complete.

xilinx.support and google gave nothing... what step should I follow to solve this one????

thanks for help!

"john wo" <j...@gmail.com>
schrieb im Newsbeitrag
news:ee8ef27.-1...@webx.sUN8CHnE...
> what about this error?
>
> --------------------------------- 
INTERNAL_ERROR:Xst:cmain.c:3022:1.146.4.1 - To resolve this error, please
consult the Answers Database and other online resources at
<http://support.xilinx.com>; ERROR: XST failed Process "Synthesize" did
not
complete.
>
> xilinx.support and google gave nothing... what step should I follow to
solve this one????
>
> thanks for help!

you need to open a WebCase, and wait for their response.
nothing more you can do, its a fatal error.

Antti

xilinx internal software error.
nothing you can do, just call Xilinx and hope for the best...

but sometimes you can have a temporary "work-around", like
disabling flattening hierarchy or timing-driven packing, etc... until a new 
SP comes out

Vladislav


"john wo" <j...@gmail.com> wrote in message 
news:ee8ef27.-1...@webx.sUN8CHnE...
> what about this error?
>
> ---------------------------------  
> INTERNAL_ERROR:Xst:cmain.c:3022:1.146.4.1 - To resolve this error, please 
> consult the Answers Database and other online resources at 
> <http://support.xilinx.com>; ERROR: XST failed Process "Synthesize"
did not 
> complete.
>
> xilinx.support and google gave nothing... what step should I follow to 
> solve this one????
>
> thanks for help! 

john wo wrote:
> what about this error?
> 
> --------------------------------- INTERNAL_ERROR:Xst:cmain.c:3022:1.146.4.1 - To
resolve this error, please consult the Answers Database and other online resources at
<http://support.xilinx.com>; ERROR: XST failed Process "Synthesize" did not
complete.
> 
> xilinx.support and google gave nothing... what step should I follow to solve this
one????
> 
> thanks for help!


Hi John


I already came across with this kind of error before (ISE 6.3), which 
appeared just after entering the "HDL Analysis" task (second step 
performed by XST after "HDL Compilation").

After spending a fair amount of time trying to isolate what triggers 
this error, I found out that it was a mismatch between a port 
declaration in an entity, and the port declaration of the related 
component in the upper level of the hierarchy (in a VHDL design).


Therefore my advice will be to try to compile your design with an other 
parser/compiler (such as Modelsim, who seems more strict than XST), and 
make sure that no suspicious warnings remain.