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Comp.Arch.FPGA | JTAG port access in Cyclone
There are 13 messages in this thread.
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JTAG port access in Cyclone - Jedi - 2005-06-21 11:50:00
hello Is there any example of how to add JTAG port support into own non-SOPC builder design like I can directly access SPI config port? For example I want to read/set own register word from an own JTAG tool. thx rick
Re: JTAG port access in Cyclone - Jedi - 2005-06-21 16:36:00
Jedi wrote: > hello > > > Is there any example of how to add JTAG port support into > own non-SOPC builder design like I can directly access > SPI config port? > > For example I want to read/set own register word from > an own JTAG tool. > Okay..getting some own defined bitstream out of JTAG port when assigning something to "tdouser"... But still unclear now what those JTAG IR exactly do: 0000001100 0000001101 0000001110 Any more documentation about this? Or is this some high-security risk NDA stuff? thx rick______________________________
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Re: JTAG port access in Cyclone - Antti Lukats - 2005-06-22 02:15:00
"Jedi" <m...@aol.com> schrieb im Newsbeitrag news:cT_te.335$N...@read3.inet.fi... > Jedi wrote: > > hello > > > > > > Is there any example of how to add JTAG port support into > > own non-SOPC builder design like I can directly access > > SPI config port? > > > > For example I want to read/set own register word from > > an own JTAG tool. > > > > Okay..getting some own defined bitstream out of JTAG port > when assigning something to "tdouser"... > > But still unclear now what those JTAG IR exactly do: > > 0000001100 > 0000001101 > 0000001110 > > Any more documentation about this? > Or is this some high-security risk NDA stuff? > > thx > rick > the documentation is almost non existant, I documented some useage of the altera bscan with some examples should be somewhere in http://gforge.openchip.org I was thinking that ony C (..001100) is the USER functions but hm you say D , E are as well ? no information about the D, E instructions, the quartus memory programmer uses C instruction that where I found it by doing trace on JTAG antti
Re: JTAG port access in Cyclone - Antti Lukats - 2005-06-22 02:32:00
"Jedi" <m...@aol.com> schrieb im Newsbeitrag news:cT_te.335$N...@read3.inet.fi... > Jedi wrote: > > hello > > > > > > Is there any example of how to add JTAG port support into > > own non-SOPC builder design like I can directly access > > SPI config port? > > > > For example I want to read/set own register word from > > an own JTAG tool. > > > > Okay..getting some own defined bitstream out of JTAG port > when assigning something to "tdouser"... > > But still unclear now what those JTAG IR exactly do: > > 0000001100 > 0000001101 > 0000001110 > > Any more documentation about this? > Or is this some high-security risk NDA stuff? > > thx > rick > http://wiki.openchip.org/index.php/Altera:JTAG uups I used 1110 0x0E instruction not 0x0D as I previously posted Antti______________________________
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Re: JTAG port access in Cyclone - Jedi - 2005-06-22 03:23:00
Antti Lukats wrote: > "Jedi" <m...@aol.com> schrieb im Newsbeitrag > news:cT_te.335$N...@read3.inet.fi... > >>Jedi wrote: >> >>>hello >>> >>> >>>Is there any example of how to add JTAG port support into >>>own non-SOPC builder design like I can directly access >>>SPI config port? >>> >>>For example I want to read/set own register word from >>>an own JTAG tool. >>> >> >>Okay..getting some own defined bitstream out of JTAG port >>when assigning something to "tdouser"... >> >>But still unclear now what those JTAG IR exactly do: >> >>0000001100 >>0000001101 >>0000001110 >> >>Any more documentation about this? >>Or is this some high-security risk NDA stuff? >> >>thx >>rick >> > > http://wiki.openchip.org/index.php/Altera:JTAG > > uups I used 1110 0x0E instruction not 0x0D as I previously posted > Correction (o; instruction 0000001101 is CONFIG_IO as documented in BSD file... Used 0000001100 last night for shifting out own shift register content successfully... As the TCK/TMS/TDI signals are also available in the module... probably this would mean I could also use unused IR codes with own TAP controller? Now have to wait for EBV Finland returning my other NIOS board for signal capturing (o; greets rick______________________________
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Re: JTAG port access in Cyclone - Jedi - 2005-06-22 03:25:00
Jedi wrote: > Antti Lukats wrote: > >> "Jedi" <m...@aol.com> schrieb im Newsbeitrag >> news:cT_te.335$N...@read3.inet.fi... >> >>> Jedi wrote: >>> >>>> hello >>>> >>>> >>>> Is there any example of how to add JTAG port support into >>>> own non-SOPC builder design like I can directly access >>>> SPI config port? >>>> >>>> For example I want to read/set own register word from >>>> an own JTAG tool. >>>> >>> >>> Okay..getting some own defined bitstream out of JTAG port >>> when assigning something to "tdouser"... >>> >>> But still unclear now what those JTAG IR exactly do: >>> >>> 0000001100 >>> 0000001101 >>> 0000001110 >>> >>> Any more documentation about this? >>> Or is this some high-security risk NDA stuff? >>> >>> thx >>> rick >>> >> >> http://wiki.openchip.org/index.php/Altera:JTAG >> >> uups I used 1110 0x0E instruction not 0x0D as I previously posted >> > > Correction (o; > > instruction 0000001101 is CONFIG_IO as documented in BSD file... > > Used 0000001100 last night for shifting out own shift register content > successfully... > > As the TCK/TMS/TDI signals are also available in the module... > probably this would mean I could also use unused IR codes with > own TAP controller? > > > Now have to wait for EBV Finland returning my other NIOS board > for signal capturing (o; > One strange thing...jtag discovery tool reports DR chain length of "7" for IR 0x00E: Detecting DR length for IR 0000001110 ... 7 For 0x00C and 0x00D it shows normal "has to be defined" behaviour: Detecting DR length for IR 0000001100 ... -1 Detecting DR length for IR 0000001101 ... -1 rick______________________________
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Re: JTAG port access in Cyclone - Antti Lukats - 2005-06-22 04:13:00
"Jedi" <m...@aol.com> schrieb im Newsbeitrag news:xn8ue.45$K...@read3.inet.fi... > Jedi wrote: > > Antti Lukats wrote: > > > >> "Jedi" <m...@aol.com> schrieb im Newsbeitrag > >> news:cT_te.335$N...@read3.inet.fi... > >> > >>> Jedi wrote: > >>> > >>>> hello > >>>> > >>>> > >>>> Is there any example of how to add JTAG port support into > >>>> own non-SOPC builder design like I can directly access > >>>> SPI config port? > >>>> > >>>> For example I want to read/set own register word from > >>>> an own JTAG tool. > >>>> > >>> > >>> Okay..getting some own defined bitstream out of JTAG port > >>> when assigning something to "tdouser"... > >>> > >>> But still unclear now what those JTAG IR exactly do: > >>> > >>> 0000001100 > >>> 0000001101 > >>> 0000001110 > >>> > >>> Any more documentation about this? > >>> Or is this some high-security risk NDA stuff? > >>> > >>> thx > >>> rick > >>> > >> > >> http://wiki.openchip.org/index.php/Altera:JTAG > >> > >> uups I used 1110 0x0E instruction not 0x0D as I previously posted > >> > > > > Correction (o; > > > > instruction 0000001101 is CONFIG_IO as documented in BSD file... > > > > Used 0000001100 last night for shifting out own shift register content > > successfully... > > > > As the TCK/TMS/TDI signals are also available in the module... > > probably this would mean I could also use unused IR codes with > > own TAP controller? > > > > > > Now have to wait for EBV Finland returning my other NIOS board > > for signal capturing (o; > > > > One strange thing...jtag discovery tool reports DR chain length > of "7" for IR 0x00E: > > Detecting DR length for IR 0000001110 ... 7 > > For 0x00C and 0x00D it shows normal "has to be defined" behaviour: > > Detecting DR length for IR 0000001100 ... -1 > Detecting DR length for IR 0000001101 ... -1 > > > > rick jtag discovery tool? which one do you mean? the 0x0E is defenetly "the" USER instruction it should be 'Open' when device is unconfigured.. the JTAG pins are not all directly accessible so you can not add your own Instructions but on the Altera you can monitor full traffic on the JTAG that passes by (that is not available on Xilinx at least pre V4) antti
Re: JTAG port access in Cyclone - Jedi - 2005-06-22 04:37:00
Antti Lukats wrote: > "Jedi" <m...@aol.com> schrieb im Newsbeitrag > news:xn8ue.45$K...@read3.inet.fi... > >>Jedi wrote: >> >>>Antti Lukats wrote: >>> >>> >>>>"Jedi" <m...@aol.com> schrieb im Newsbeitrag >>>>news:cT_te.335$N...@read3.inet.fi... >>>> >>>> >>>>>Jedi wrote: >>>>> >>>>> >>>>>>hello >>>>>> >>>>>> >>>>>>Is there any example of how to add JTAG port support into >>>>>>own non-SOPC builder design like I can directly access >>>>>>SPI config port? >>>>>> >>>>>>For example I want to read/set own register word from >>>>>>an own JTAG tool. >>>>>> >>>>> >>>>>Okay..getting some own defined bitstream out of JTAG port >>>>>when assigning something to "tdouser"... >>>>> >>>>>But still unclear now what those JTAG IR exactly do: >>>>> >>>>>0000001100 >>>>>0000001101 >>>>>0000001110 >>>>> >>>>>Any more documentation about this? >>>>>Or is this some high-security risk NDA stuff? >>>>> >>>>>thx >>>>>rick >>>>> >>>> >>>>http://wiki.openchip.org/index.php/Altera:JTAG >>>> >>>>uups I used 1110 0x0E instruction not 0x0D as I previously posted >>>> >>> >>>Correction (o; >>> >>>instruction 0000001101 is CONFIG_IO as documented in BSD file... >>> >>>Used 0000001100 last night for shifting out own shift register content >>>successfully... >>> >>>As the TCK/TMS/TDI signals are also available in the module... >>>probably this would mean I could also use unused IR codes with >>>own TAP controller? >>> >>> >>>Now have to wait for EBV Finland returning my other NIOS board >>>for signal capturing (o; >>> >> >>One strange thing...jtag discovery tool reports DR chain length >>of "7" for IR 0x00E: >> >>Detecting DR length for IR 0000001110 ... 7 >> >>For 0x00C and 0x00D it shows normal "has to be defined" behaviour: >> >>Detecting DR length for IR 0000001100 ... -1 >>Detecting DR length for IR 0000001101 ... -1 >> >> >> >>rick > > > jtag discovery tool? which one do you mean? Using the jtag tools from the openwince project at sf.net. Great for boundary scan flashing and testing since you can add your own ir/dr definitions and get/set/reset individual boundary scan registers. > > the 0x0E is defenetly "the" USER instruction it should be 'Open' when device > is unconfigured.. Hmm..might be NIOS2 config gets switched back residing in SPI during discovery (o; > > the JTAG pins are not all directly accessible so you can not add your own > Instructions > but on the Altera you can monitor full traffic on the JTAG that passes by > (that is not available on Xilinx at least pre V4) How about Lattice? rick
Re: JTAG port access in Cyclone - Jedi - 2005-06-22 04:57:00
Antti Lukats wrote: > "Jedi" <m...@aol.com> schrieb im Newsbeitrag > news:xn8ue.45$K...@read3.inet.fi... > > > jtag discovery tool? which one do you mean? > > the 0x0E is defenetly "the" USER instruction it should be 'Open' when device > is unconfigured.. Erased SPI config memory..now correctly showing: Detecting DR length for IR 0000001100 ... -1 Detecting DR length for IR 0000001110 ... -1 And both returning same preloaded 8-bit shift register: Device Id: 00000010000010000100000011011101 Manufacturer: Altera Part: EP1C20F400 Stepping: 0 Filename: /usr/local/share/jtag/altera/ep1c20f400/ep1c20f400 Setting TCK frequency to 2 Hz jtag> instruction IR1100 jtag> shift ir jtag> shift dr jtag> dr 01101111 jtag> instruction IR1110 jtag> shift ir jtag> shift dr jtag> dr 01101111 jtag> rick______________________________
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Re: JTAG port access in Cyclone - Antti Lukats - 2005-06-22 10:12:00
"Jedi" <m...@aol.com> schrieb im Newsbeitrag news:hK9ue.71$K...@read3.inet.fi... > Antti Lukats wrote: > > "Jedi" <m...@aol.com> schrieb im Newsbeitrag > > news:xn8ue.45$K...@read3.inet.fi... > > > > > > jtag discovery tool? which one do you mean? > > > > the 0x0E is defenetly "the" USER instruction it should be 'Open' when device > > is unconfigured.. > > Erased SPI config memory..now correctly showing: > > Detecting DR length for IR 0000001100 ... -1 > Detecting DR length for IR 0000001110 ... -1 > > And both returning same preloaded 8-bit shift register: > > Device Id: 00000010000010000100000011011101 > Manufacturer: Altera > Part: EP1C20F400 > Stepping: 0 > Filename: /usr/local/share/jtag/altera/ep1c20f400/ep1c20f400 > Setting TCK frequency to 2 Hz > jtag> instruction IR1100 > jtag> shift ir > jtag> shift dr > jtag> dr > 01101111 > jtag> instruction IR1110 > jtag> shift ir > jtag> shift dr > jtag> dr > 01101111 > jtag> > > > rick look in MAX2 datasheet there are USER0 and USER1 defined !! I did not know ! Antti