Sign in

username:

password:



Not a member?

Search Comp.Arch.FPGA



Search tips

fpga by Keywords

Altera | ASIC | CPLD | Cyclone | DCM | DDR | DSP | Ethernet | ISE | JTAG | Linux | LVDS | Microblaze | ML310 | Modelsim | NIOS | OPB | PCI | Quartus | RocketIO | SDRAM | Spartan | Spartan3 | SRAM | Stratix | Verilog | VHDL | Virtex | Virtex-4 | Virtex-II | Xilinx | XST


Ads

See Also

DSPEmbedded SystemsElectronics

Comp.Arch.FPGA | Problem with user defined logicinterface in Nios

There are 1 messages in this thread.

You are currently looking at messages 0 to 1.

Problem with user defined logicinterface in Nios - Thorsten Klatt - 2003-07-07 07:50:00

Hi,
 I am using Quartus 2.2 SP2 with Nios 3.0

I have fit my logic with the SOPC into the Niosstructure and generating and
compiling of this is fine.
I am testing on a stratix devel. board. Programming of the fpga works out
fine too.
The problem is, that no programm runs on the nios. (i.e. hello_world)
The srec file is downloaded to the chip and then just the terminal appears.
(nr -r hello_world.srec) After I press the CPU-Reset the nios string
appears. So it seems like the programm is running in an endless loop.
If  I use the nios-consol I am able to access the peripherie, like turning
on/off the leds in writing directly to the addresses.

By the way, without my logic the nios executes the code.
Has anyone an idea what the reason could be ?

Thanks Thorsten