Hi all,

I'm using a Spartan 3 test board with a xc3s200 fpga. Before, I used a
larger device (Virtex II ) and had no problems with my design (microblaze
with my own IP, connected to the OPB-bus). But now, I get errors during the
map process due to the small amount of slices... --> it seems that the
device is too small. But: when I don't connect my IP with the OPB,
everything's fine. At the moment when I click in Xilinx Platform Studio on
the white square to connect to OPB that a 'S' appears , the problem with the
overmapped slices occurs. Without connection about 50% of slices are used,
connected to the OPB more than 230%.
How could that be possible??
I'm using the latest versions of ISE and XPS.

Thanks in advance,

Stefan

On Fri, 22 Jul 2005 16:39:38 +0200,
"Stefan" <h...@hotmail.com> wrote:
>Hi all,
>
>I'm using a Spartan 3 test board with a xc3s200 fpga. Before, I used a
>larger device (Virtex II ) and had no problems with my design (microblaze
>with my own IP, connected to the OPB-bus). But now, I get errors during the
>map process due to the small amount of slices... --> it seems that the
>device is too small. But: when I don't connect my IP with the OPB,
>everything's fine. At the moment when I click in Xilinx Platform Studio on
>the white square to connect to OPB that a 'S' appears , the problem with the
>overmapped slices occurs. Without connection about 50% of slices are used,
>connected to the OPB more than 230%.
>How could that be possible??

The software may be trimming logic from your design when you don't have
the IP connected. For an unrelated example, if you had a design that was
1000 slices, and the end result is a single signal, connected to an IOB,
and all the rest of the IOBs are inputs. Assuming no other issues, this
design places and routes and uses 1000 slices. If you then make a change
that just does not connect the output to the IOB, the whole design would
be trimmed, and zero slices used.

What happens is that the SW deletes logic that cannot change the external
behavior of the chip. So what happens is the logic that generates the
final signal is trimmed. Then the logic that was feeding it is now not
driving anything, and it is trimmed, and this continues all the way back
to the inputs.

In your design, if the IP is not connected to the OPB, then all its
outputs can be trimmed, and then work back to the start of the IP. If
there are no other outputs of the IP, the whole thing could be trimmed.
Same thing is true of the OPB. Also trimming can start at the input end
of a design. If an input does not connect to an IOB, or it is a constant,
then logic trimming can start at the input end, and work forward towards
the output.

The trimming report is the place to start examining this issue.

>I'm using the latest versions of ISE and XPS.
>
>Thanks in advance,
>
>Stefan
>


Philip
Philip Freidin
Fliptronics