We're about to move an existing design to an
ASIC.  The prototype was
built using a small PIC and some discretes, so the ASIC will look
nothing like the prototype.

I'm looking for some suggestions for ASIC design house people have used
and been happy with as well as ASIC design services (someone able to
take a project successfully from concept through production), should we
decide to use outside services.

There are too many issues to detail here, but here are a few:
- Super-low power, we're looking for aggressive sleep mode, low power
while running, some kind of built-in RC oscillator if that's possible
(4MHz and 32KHz and off).
- Low voltage would be ideal 1.5 - 1.8 volts or thereabouts.
- Need some beefy I/O lines if possible 15-25ma
- The application itself is reasonably straight-forward, we need a
UART, a state machine, some switch debouncing, jelly-bean stuff like
that, as well as some kind of ROM space a few K and some RAM a hundred
bytes or so.

The more I think about the problem, the more it seems like a custom
micro-controller.  Any thoughts?

Thanks,
Dave.

Dear Dave,
why not use a FPGA or a CPLD instead of an ASIC?
the Spartan3 and coolrunner (from Xilinx) for example seems reasonable
cheep.
The advantage using  FPGA are:
1. reduced risk (if you do a mistake you can fix it even after the
production and distribution)
2. the costs in the design are lower (much lower)
3. the time to market is shorter

If the application is so straight forward maybe a CPLD like coolrunner
is enougth.
Also another advantage iss that now you can download all the SW you
need to program and simulate the CPLD and many FPGA from the Xilinx
Website for free and in my experience the tool ISE7.1 is now very very
stable.

Regards,
Francesco

Don't overlook Altera's HardCopy program
(analogous to a structured ASIC), 
for FPGA's.  I've seem some pretty impressive numbers, especially in the 
HardCopyII program.  You can go right from FPGA to HardCopy and have your 
timings guaranteed.  Engineers often forget about the cycles need to verify 
the ASIC's timings, etc.

The other nice thing is that the footprints for both the FPGA and the 
HardCopy device can be backward compatible. The company I work for is 
currently going through the process and it is as easy as Altera claims it 
is.  And as Francesco said, the time to market is much quicker than turning 
around a full ASIC.


<f...@trendcomms.com> wrote in message 
news:1...@g49g2000cwa.googlegroups.com...
> Dear Dave,
> why not use a FPGA or a CPLD instead of an ASIC?
> the Spartan3 and coolrunner (from Xilinx) for example seems reasonable
> cheep.
> The advantage using  FPGA are:
> 1. reduced risk (if you do a mistake you can fix it even after the
> production and distribution)
> 2. the costs in the design are lower (much lower)
> 3. the time to market is shorter
>
> If the application is so straight forward maybe a CPLD like coolrunner
> is enougth.
> Also another advantage iss that now you can download all the SW you
> need to program and simulate the CPLD and many FPGA from the Xilinx
> Website for free and in my experience the tool ISE7.1 is now very very
> stable.
>
> Regards,
> Francesco
> 

If FPGA/CPLDs don't meet your power requirement,
you need to first
think about the kind of process you want to use. With your tiny gate
count on an up-to-date process your chip will be mostly blank and
dominated by pads. You cost will be in testing and packaging. Best bet
is to find an off-the-shelf solution or one of those "structured"
ASICs.

dave94024 wrote:
> We're about to move an existing design to an ASIC.  The prototype was
> built using a small PIC and some discretes, so the ASIC will look
> nothing like the prototype.
>
> I'm looking for some suggestions for ASIC design house people have used
> and been happy with as well as ASIC design services (someone able to
> take a project successfully from concept through production), should we
> decide to use outside services.
>
> There are too many issues to detail here, but here are a few:
> - Super-low power, we're looking for aggressive sleep mode, low power
> while running, some kind of built-in RC oscillator if that's possible
> (4MHz and 32KHz and off).
> - Low voltage would be ideal 1.5 - 1.8 volts or thereabouts.
> - Need some beefy I/O lines if possible 15-25ma
> - The application itself is reasonably straight-forward, we need a
> UART, a state machine, some switch debouncing, jelly-bean stuff like
> that, as well as some kind of ROM space a few K and some RAM a hundred
> bytes or so.
>
> The more I think about the problem, the more it seems like a custom
> micro-controller.  Any thoughts?
> 
> Thanks,
> Dave.

Thanks for all the replies.

This is for very high volume production where cost and low-power are
nearly everything.  Which rules out (I think) pretty much all FPGA and
CPLD solutions and may even marginalize structured ASIC solutions (not
sure about this).

Actually the more I think about it, the more I'm considering just
buying die for the microcontroller and encapsulating all of our
specialized glue logic in a small ASIC (we're looking at a few thousand
gates tops).

The plusses are that we won't be reinventing the wheel (as far as the
micro goes, at least not in initial production we could always
cost-reduce later).  The micro may need to change for several different
applications.

Does anyone have any good ASIC fabs to suggest?

Dave.

Dave,

Don't rule out CoolRunner II.  We are used in cell phones (to fix the 
ASIC bugs on a regular basis).

Can not think of any tougher low power application than that.

By the way, if you go to the cell phone ASIC vendor's websites, they 
detail all the errata, and all the little logic circuits needed to work 
around their bugs.  Seems like we can get Coolrunner II designed into 
every first run of every cell phone pcb....

Not a bad business, fixing other people's ASIC goofs.

Austin

dave94024 wrote:

> Thanks for all the replies.
> 
> This is for very high volume production where cost and low-power are
> nearly everything.  Which rules out (I think) pretty much all FPGA and
> CPLD solutions and may even marginalize structured ASIC solutions (not
> sure about this).
> 
> Actually the more I think about it, the more I'm considering just
> buying die for the microcontroller and encapsulating all of our
> specialized glue logic in a small ASIC (we're looking at a few thousand
> gates tops).
> 
> The plusses are that we won't be reinventing the wheel (as far as the
> micro goes, at least not in initial production we could always
> cost-reduce later).  The micro may need to change for several different
> applications.
> 
> Does anyone have any good ASIC fabs to suggest?
> 
> Dave.
> 

Okay, we're looking for something that will work
at ~1-10ua of power
consumption at 1.5v, which makes us much lower power than cell-phones
(I'm guessing several orders of magnitude).  And we're looking for
something that is pennies to produce in large volumes.  That's why I'm
guessing we rule out CPLDs and FPGAs.

Thanks,
Dave.

Oh, forgot to mention.  That's peak power.  We
need to be in the tens
of nanoamps during sleep mode which is the bulk of the time.

Dave.

"dave94024"
<d...@sbcglobal.net> schrieb im Newsbeitrag
news:1...@z14g2000cwz.googlegroups.com...
> Oh, forgot to mention.  That's peak power.  We need to be in the tens
> of nanoamps during sleep mode which is the bulk of the time.
>
> Dave.
>

try contacting

http://www.emmicroelectronic.com

I bet they will do the job for you at your quantities

you can also try melexis, but I bet EM is better choice

Antti
BTW, thank you for your posting, thanks to it I found that EM is now also
offering SO-8 packaged MCU's that new and I did not know that before.

EM looks perfect for our application.

Thanks!
Dave.