Hello, last year there was a post concerning
Altera abandoning AHDL in
their new tools, such as Quartus. The post also said that you
couldn't use AHDL with SOPC Builder or DSP Builder. If this is true,
it seems to be a big constraint for the designer; then again, I have
yet to use SOPC or DSP Builder. How then do you write custom logic, do
you have to write everything in .vhdl or .verilog? I have a few
co-workers who used DSP Builder, but couldn't get to work correctly, it
required purchasing more software from Altera. They dropped DSP Builder
and went back to AHDL coding. Is AHDL a thing of the past? Is a better
approach SOPC and DSP Builder? If so, then I better start reading more
about these tools. Any comments on AHDL, Altera, SOPC Builder, or DSP
Building, please share them.

thanks,
joe

AHDL is a HDL just like VHDL and Verilog are.
VHDL and Verilog are open
HDL standards supported by many synthesis vendors, whereas AHDL is
proprietary to Altera. Altera will continue to support synthesis of
AHDL based designs, to ensure that legacy products using AHDL can be
recompiled using newer versions of Quartus.

DSP Builder and SOPC Builder are code generators from high level
descriptions. DSP Builder works of the Matlab/Simulink system
description and SOPC builder works of its own system description.

In the end both DSP Builder and SOPC Builder tools generate VHDL or
Verilog that is input into Quartus. We have chosen not to support AHDL
as the output of DSP Builder or SOPC Builder as the generated systems
could not be simulated using any of the standard HDL simulators like
Modelsim, VCS, NCSim etc.

If you want to use Modelsim for behavioral or timing simulation you are
better of writing your code in VHDL or Verilog instead of AHDL. If you
would like to perform timing simulation using the Quartus native gate
level simulator you can write your code in AHDL. Quartus allows mising
of languages therefore it is possible to have a mixture of VHDL
entities, Verilog modules and AHDL subdesigns within the same project.

Hope this helps,
Subroto Datta
Altera Corp.

Subroto Datta wrote:
> AHDL is a HDL just like VHDL and Verilog are. VHDL and Verilog are open
> HDL standards supported by many synthesis vendors, whereas AHDL is
> proprietary to Altera. Altera will continue to support synthesis of
> AHDL based designs, to ensure that legacy products using AHDL can be
> recompiled using newer versions of Quartus.
> 
> DSP Builder and SOPC Builder are code generators from high level
> descriptions. DSP Builder works of the Matlab/Simulink system
> description and SOPC builder works of its own system description.
> 
> In the end both DSP Builder and SOPC Builder tools generate VHDL or
> Verilog that is input into Quartus. We have chosen not to support AHDL
> as the output of DSP Builder or SOPC Builder as the generated systems
> could not be simulated using any of the standard HDL simulators like
> Modelsim, VCS, NCSim etc.
> 
> If you want to use Modelsim for behavioral or timing simulation you are
> better of writing your code in VHDL or Verilog instead of AHDL. If you
> would like to perform timing simulation using the Quartus native gate
> level simulator you can write your code in AHDL. Quartus allows mising

that should be mixing ?

> of languages therefore it is possible to have a mixture of VHDL
> entities, Verilog modules and AHDL subdesigns within the same project.

Altera could do AHDL to VHDL ?

  That is what I understand Xilinx do, on their newest webpacks, for the
ABEL flows ?
  A commendable move, as it preserves code base, expands user language 
choice, and allows hooking into the simuators you mention above.

  -jg

You can use the SOPC builder with AHDL, but you
have to write a wrapper
in VHDL or BDF. My experience is that although not happy about the
extra file to write, it works.

Havard

Jim Granville schrieb:
> Subroto Datta wrote:
>> Quartus allows mising
> that should be mixing ?

No, missing.
The OP was missing a language ;-)

Kolja Sulimma