Does anyone know how feasible it is to drive a
TFT panel LVDS interface (sometimes called Panel-link
I think) direct from the S3 I/Os ? If so, what sort of frequency can you get up to - I saw
a mention
recently about using the DDR registers to reduce the data rate but couldn't immediately
see any
Xilinx appnotes when I had a quick look.
 
Also, as the IO banks on the lower-end dev boards tend to be tied to +3.3v, but LVDS needs
2.5v,
what happens if you lie to the software about the supply - will it work to any useful
degree
(interested in lvds output only)?

Mike Harrison wrote:
> Does anyone know how feasible it is to drive a TFT panel LVDS interface (sometimes
called Panel-link
> I think) direct from the S3 I/Os ? If so, what sort of frequency can you get up to -
I saw a mention
> recently about using the DDR registers to reduce the data rate but couldn't
immediately see any
> Xilinx appnotes when I had a quick look.

Look at
http://www.xilinx.com/bvdocs/appnotes/xapp298.pdf

It's not for TFT panels but for their TX side, they serialize 10 bits by
using a 5x clock and DDR flips flops with a differential output.


> Also, as the IO banks on the lower-end dev boards tend to be tied to +3.3v, but LVDS
needs 2.5v,
> what happens if you lie to the software about the supply - will it work to any useful
degree
> (interested in lvds output only)?

Well, on lower end board, the trace might not be routed as differential
anyway. The Avnet spartan 3 board (the PCI one) I have has 4 LVDS pairs
connected on 2.5v rail.

That's definitly something I'd like to do. I might try it soon with an
old laptop scree if I find the doc for it.



	Sylvain

On Wed, 31 Aug 2005 19:04:24 +0000, Mike Harrison
wrote:

> Does anyone know how feasible it is to drive a TFT panel LVDS interface (sometimes
called Panel-link
> I think) direct from the S3 I/Os ? If so, what sort of frequency can you get up to -
I saw a mention
> recently about using the DDR registers to reduce the data rate but couldn't
immediately see any
> Xilinx appnotes when I had a quick look.
>  
> Also, as the IO banks on the lower-end dev boards tend to be tied to +3.3v, but LVDS
needs 2.5v,
> what happens if you lie to the software about the supply - will it work to any useful
degree
> (interested in lvds output only)?

Funny you should mention this - I am working on exactly this at
work right now.

It's not working right now, but the basics are in place.  clock
runs and I see data coming out of the fpga, but I think I might
be shifting bits in the wrong place.  Panel stuff is annoying in
that the data streams are organized in 7-bit chunks which means
you have to do some trickery to do shifting via the DDR registers.

The DDR trick is nice, otherwise you end up doing a fair bit
of monkeying with RLOC attributes if you want to run an s3 -4
speed grade part at 200+ Mhz.

Our board has a selectable 2.5V/3.3V bank for doing either LVTTL
or LVDS panel stuff.

I assume you know about the TTL to LVDS chips made for this from
National and others?

On Wed, 31 Aug 2005 23:49:24 -0500, Andrew Dyer
<a...@gmail.com> wrote:

>On Wed, 31 Aug 2005 19:04:24 +0000, Mike Harrison wrote:
>
>> Does anyone know how feasible it is to drive a TFT panel LVDS interface
(sometimes called Panel-link
>> I think) direct from the S3 I/Os ? If so, what sort of frequency can you get up
to - I saw a mention
>> recently about using the DDR registers to reduce the data rate but couldn't
immediately see any
>> Xilinx appnotes when I had a quick look.
>>  
>> Also, as the IO banks on the lower-end dev boards tend to be tied to +3.3v, but
LVDS needs 2.5v,
>> what happens if you lie to the software about the supply - will it work to any
useful degree
>> (interested in lvds output only)?
>
>Funny you should mention this - I am working on exactly this at
>work right now.
>
>It's not working right now, but the basics are in place.  clock
>runs and I see data coming out of the fpga, but I think I might
>be shifting bits in the wrong place.  Panel stuff is annoying in
>that the data streams are organized in 7-bit chunks which means
>you have to do some trickery to do shifting via the DDR registers.

What frequency/display format are you aiming for ? 

>The DDR trick is nice, otherwise you end up doing a fair bit
>of monkeying with RLOC attributes if you want to run an s3 -4
>speed grade part at 200+ Mhz.
>
>Our board has a selectable 2.5V/3.3V bank for doing either LVTTL
>or LVDS panel stuff.
>
>I assume you know about the TTL to LVDS chips made for this from
>National and others?

Yes - I bought a couple to play with after messing with a ttl (parallel) style interface,
but I was
wondering how possible it would be without..

On Thu, 01 Sep 2005 00:32:32 +0200, Sylvain
Munaut <com.246tNt@tnt> wrote:

>Mike Harrison wrote:
>> Does anyone know how feasible it is to drive a TFT panel LVDS interface
(sometimes called Panel-link
>> I think) direct from the S3 I/Os ? If so, what sort of frequency can you get up
to - I saw a mention
>> recently about using the DDR registers to reduce the data rate but couldn't
immediately see any
>> Xilinx appnotes when I had a quick look.
>
>Look at
>http://www.xilinx.com/bvdocs/appnotes/xapp298.pdf
>
>It's not for TFT panels but for their TX side, they serialize 10 bits by
>using a 5x clock and DDR flips flops with a differential output.
>
>
>> Also, as the IO banks on the lower-end dev boards tend to be tied to +3.3v, but
LVDS needs 2.5v,
>> what happens if you lie to the software about the supply - will it work to any
useful degree
>> (interested in lvds output only)?
>
>Well, on lower end board, the trace might not be routed as differential
>anyway. The Avnet spartan 3 board (the PCI one) I have has 4 LVDS pairs
>connected on 2.5v rail.
>
>That's definitly something I'd like to do. I might try it soon with an
>old laptop scree if I find the doc for it.

TFT panel docs are a bit scarce but from what I've seen, they are all very similar to each
other
within any given resolution. If you have the whole laptop lid, you will have the
cable/flexi which
will help identify the connections. 
Here are some links to tft pinouts and data I found a while ago. Most concern ttl-style
panels but
even the LVDS ones are based on this, so give a starting point for experimenting with
timings etc.
Some LVDS panels have an  identifiable LVDS-to-TTL converter chip, so the pinouts can be
derived by
beeping out the pins.
 
http://www.optrex.com/products/groupdetail.asp?g=TFT&s=12.1
http://www.linux-hacker.net/cgi-bin/UltraBoard/UltraBoard.pl?Action=ShowPost&Board=ver
ytech&Post=152&Idle=0&Sort=0&Order=Descend&Page=0&Session=
http://support.advantech.com.tw/Cservice/LCD.nsf/f99b88c84af1eeff482565ec000759ea?OpenView
&Start=1&Count=30&Expand=17.1#17.1

On Thu, 01 Sep 2005 08:26:47 +0000, Mike Harrison
wrote:
> 
> What frequency/display format are you aiming for ? 

800x600 10.4" 18-bit color.  Right now I'm using a
pixel clock of 28 MHz with an eye to around 40MHz
after resolving some other issues in the design
that we copied from old stuff.

We should have something for you in Raggedstone1
when it launches if you 
want to play with this.

John Adair
Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development 
Board.
http://www.enterpoint.co.uk

"Mike Harrison" <m...@whitewing.co.uk> wrote in message 
news:6...@4ax.com...
> Does anyone know how feasible it is to drive a TFT panel LVDS interface 
> (sometimes called Panel-link
> I think) direct from the S3 I/Os ? If so, what sort of frequency can you 
> get up to - I saw a mention
> recently about using the DDR registers to reduce the data rate but 
> couldn't immediately see any
> Xilinx appnotes when I had a quick look.
>
> Also, as the IO banks on the lower-end dev boards tend to be tied to 
> +3.3v, but LVDS needs 2.5v,
> what happens if you lie to the software about the supply - will it work to 
> any useful degree
> (interested in lvds output only)?