Hello fpga-faq,

I want to create a user module that will act as a master on an opb bus.
 I am using xilinx Platform Studio, version 7.1i. Now before you say
it, I have read the http://www.xilinx.com/ise/embedded/est_rm.pdf guide
on using the create/import wizard for xps.  I have read it, and seen
the skeleton, but have not been successful with a master bus.  I have
created a custom slave module, and succeeded...
Has anyone done this?  I just want some sample code that does anything
as a master on an opb bus.
In case it is not clear why this would be a good thing, there are many
edk tools that will only work over an opb bus- but in many fpga
designs, you don't really need a processor, just custom code.  All I
want is the edk uartlite over a opb bus, but I have to be the opb
master to do it.

thank you,
~arin

a...@hotmail.com wrote:
> Hello fpga-faq,
>
> I want to create a user module that will act as a master on an opb bus.

I have not had much luck with the Xilinx tools for creating
peripherals.
I would just read
http://www-306.ibm.com/chips/techlib/techlib.nsf/techdocs/9A7AFA74DAD200D087256AB30005F0C8
/$file/OpbBus.pdf
(search for opbbus.pdf on www.ibm.com)
and write it by hand.  Of course, if all you need is a uart there is
plenty of source.

Alan Nishioka

I'm the guy that usually says to use the wizard
but its not appropriate
for your case.  Directly implementing an opb master is quite
straightforward--plb is more complicated.  The CoreConnect OPB Bus
specification will give you all the signals, but OPB has a pretty simple
request-grant scheme.

A colleague created a master in HDL to interface with the opb_ddr
controller.  It was only a couple of lines of code.  

Paul 

"a...@hotmail.com" wrote:
> 
> Hello fpga-faq,
> 
> I want to create a user module that will act as a master on an opb bus.
>  I am using xilinx Platform Studio, version 7.1i. Now before you say
> it, I have read the http://www.xilinx.com/ise/embedded/est_rm.pdf guide
> on using the create/import wizard for xps.  I have read it, and seen
> the skeleton, but have not been successful with a master bus.  I have
> created a custom slave module, and succeeded...
> Has anyone done this?  I just want some sample code that does anything
> as a master on an opb bus.
> In case it is not clear why this would be a good thing, there are many
> edk tools that will only work over an opb bus- but in many fpga
> designs, you don't really need a processor, just custom code.  All I
> want is the edk uartlite over a opb bus, but I have to be the opb
> master to do it.
> 
> thank you,
> ~arin

Hi ,
      Do u have Xilinx EDK 6.2 tools, in case u have them then , if u
go to /hw/XilinxReferenceDesigns/pcores/opb_core_msp0_v1_00_b/ , thats
nothing but a OPB Bus Master design with Write capability. The only
catch is that it uses a very old version of IPIF. If you are ok with
that then you can go ahead and use it.
       In case u dont have EDK 6.2 , then just send me an e-mail and I
can tar the file and send it to you ..

--
Parag Beeraka