Hello:

Has anyone actually gotten the master functionality in the PLB IPIF to 
work correctly?  I have been making slave peripherals without a problem.

I have an application where I am trying to directly transfer 64-bit data 
from my peripheral to DDR ram. This problem came about as the PowerPC in 
the Virtex II pro requires 2 bus reads and writes to move 64-bit data 
around.  I have the problem that I hneed to stream multiple channels of 
data into my DDR Ram and CPU intervention would be just too slow.


Here is my hardware setup:

I have the Digilent VirtexII Pro develop board with a 512MB DIMM 
Installed.  (This memory has been verfied to work with extensive memory 
tests). The DDR RAM starts at address 0x000000000.

Here is my problem. I used the create peripheral wizard to create a 
simple PLB peripheral is User SW register support and simple master 
support.

I could find very little documentation on the master interface except 
for a timing diagram on a Master Burst read and write operation.


I have very simple logic the upon a trigger (write to one register) will 
initiate a state machine to start a master operation.  I give the master 
attachment static addresses for where the data is and where needs to end 
up.  I always get the Bus2IP_MstLastAck signal indicating that 
everything is all done but the data never gets transfered.  I try to 
verify the operation by looking at my target address to see if data ever 
makes it (which it doesn't)

Does anyone out there have any experience with this?


Also, I notice that IPIF master operations always take 2 transactions. 
If I want to write to a location, it first does a local read to get data 
and a remote write to send the data. It would be nice is there was a 
single transaction interface.  I already have the 64-bit data ready.  I 
just want to provide it to the interface and have it directly send the 
data without a bus read.


-Eli

Eli Hughes wrote:
> Has anyone actually gotten the master functionality in the PLB IPIF to
> work correctly?  I have been making slave peripherals without a problem.


I have not had much luck with the Xilinx tools for creating
peripherals.  I tried and failed to use ipif to create a plb master.

I would just read
http://www-306.ibm.com/chips/techlib/techlib.nsf/techdocs/8BA965C773B2E0ED87256AB20082CC9F
/$file/64bitPlbBus.pdf
(search for 64bitplbbus.pdf on www.ibm.com)
and write it by hand.  This worked great for me.

Alan Nishioka

a...@nishioka.com wrote:
> Eli Hughes wrote:
> 
>>Has anyone actually gotten the master functionality in the PLB IPIF to
>>work correctly?  I have been making slave peripherals without a problem.
> 
> 
> 
> I have not had much luck with the Xilinx tools for creating
> peripherals.  I tried and failed to use ipif to create a plb master.
> 
> I would just read
>
http://www-306.ibm.com/chips/techlib/techlib.nsf/techdocs/8BA965C773B2E0ED87256AB20082CC9F
/$file/64bitPlbBus.pdf
> (search for 64bitplbbus.pdf on www.ibm.com)
> and write it by hand.  This worked great for me.
> 
> Alan Nishioka
> 


Did you have to do anything special such that the module is detected in 
platform studio?  I am assumming that I can just use all the signal 
names in the top-level module that the xilinx module provides when I use 
the wizard and PLatform studio will hook everything up.

-Eli

To create a module in platform studio, you have
to create a directory
structure in the project subdirectory pcores/
This includes .pao, .mpd, files in data/ that describe connections.
I copied and modified this from a core that had similar features to
what I wanted.
I was never able to get the wizard to do what I wanted, so I don't have
much experience with it.

Alan Nishioka