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Comp.Arch.FPGA | Problems with phase shift dcm
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Problems with phase shift dcm - 2005-10-11 05:19:00
Description of the problem: I use a spartan 3-400 FPGA. A clk_100 (100 MHz), generated by a DCM is coming out of the FPGA and is used as an input for the phase shift DCM (clk100_fs). This construction is made to eliminate board skew. When I measure the clk100_fs it is not what I expect. (the phase shift is not according to the spec) When I change the input of the phase shift DCM to the clk_100 internal it is working correctly. I don't know what the problem is? Can you do only a phase shift with a clock which is generated by a DCM?
