How much does it cost to produce an ASIC?  This
is for a
simple customized 8-bit CPU and 64KB of on-chip RAM.

If it is already working in an FPGA, can I count on the
ASIC also working?

Can I just hand the VHDL/Verilog files to the fabricator? Or
should I change the design to take advantage of ASIC features
(like maybe gated clocks to reduce power consumption).

If you have moved a design from FPGA to ASIC, how difficult
was the process?  What did you gain in terms of speed and/or
power consumption?

Both Xilinx and Altera has options to move to
ASIC-like implementations
from FPGA designs. These chips have a lower unit cost.

Xilinx calls it EasyPath Solution :
http://www.xilinx.com/products/silicon_solutions/fpgas/easypath/index.htm
.
Altera calls it Hardcopy
http://www.altera.com/products/devices/hardcopyii/hr2-index.jsp

Kunal wrote:
> Both Xilinx and Altera has options to move to ASIC-like implementations
> from FPGA designs. These chips have a lower unit cost.
>
> Xilinx calls it EasyPath Solution :
> http://www.xilinx.com/products/silicon_solutions/fpgas/easypath/index.htm
> .
> Altera calls it Hardcopy
> http://www.altera.com/products/devices/hardcopyii/hr2-index.jsp

Very interesting.  The Xilinx "EasyPath" seems to be a partialy
pre-programmed FPGA.  The main (only?) benefit appears to be lower
unit cost.  There is no power or performance benefit over a standard
FPGA.

The Altera "Hardcopy" is closer to a real ASIC, but the up-front costs
are also much higher.  It will run faster and use less power (~50%)
than the same logic in an FPGA.

The up-front cost for "EasyPath" is about $75,000.
The up-front cost for "Hardcopy" is about $500,000.

Both of these costs are from Xilinx's website.  Altera's site mentions
no prices.

Both companies guarantee than if the design works in the FPGA, it will
work the same or better in the "ASIC".

>
> The Altera "Hardcopy" is closer to a real ASIC, but the up-front costs
> are also much higher.  It will run faster and use less power (~50%)
> than the same logic in an FPGA.
>
> The up-front cost for "EasyPath" is about $75,000.
> The up-front cost for "Hardcopy" is about $500,000.

Are you sure? I have heard figures of less than half that, but then again my 
memory is not what it used to be so I could be wrong :-)

Hans.
www.ht-lab.com

> How much does it cost to produce an ASIC?

Depends on the process. For .18, expect to pay $200k.

> If it is already working in an FPGA, can I count on the ASIC also working?

No. Lots more things can go wrong when making an ASIC.

> Can I just hand the VHDL/Verilog files to the fabricator?

Depends on the fab. Some will do it, some won't. For those that don't,
there are plenty of design services companies that will do it for you.

> Or should I change the design to take advantage of ASIC features

Depends on your performance requirements.

> If you have moved a design from FPGA to ASIC, how difficult was the process?

Fairly easy, but that's because I've always planned ahead, and not used
many FPGA specific features. That way, the only things you need to
change are memories and I/Os.

> What did you gain in terms of speed

Virtex II Pro -7: 150MHz - .13 ASIC - 400 MHz.

> power consumption?

Huge amounts. FPGAs suck current like there's no tomorrow.

Cheers,
Jon

Hans wrote:
> >
> > The Altera "Hardcopy" is closer to a real ASIC, but the up-front
costs
> > are also much higher.  It will run faster and use less power (~50%)
> > than the same logic in an FPGA.
> >
> > The up-front cost for "EasyPath" is about $75,000.
> > The up-front cost for "Hardcopy" is about $500,000.
>
> Are you sure? I have heard figures of less than half that, but then again my
> memory is not what it used to be so I could be wrong :-)

I am fairly sure about the "EasyPath" cost, since that is from
Xilinx's own website.

I am not at all sure about the "Hardcopy" cost, since that is from
Xilinx's website too, not Altera's (as I mentioned in my post).
Xilinx's cost estimate may put Altera's product in an unfavorable
light, but it serves them right.  If they want accurate information
disseminated, they should provide the information themselves.  I
could find no price information anywhere on Altera's website.

Anyway, here is my source of information for the cost of both products:

http://www.xilinx.com/products/silicon_solutions/fpgas/easypath/overview.htm

"Kunal" <k...@gmail.com>
schrieb im Newsbeitrag
news:1...@g49g2000cwa.googlegroups.com...
> Both Xilinx and Altera has options to move to ASIC-like implementations
> from FPGA designs. These chips have a lower unit cost.
>
> Xilinx calls it EasyPath Solution :
> http://www.xilinx.com/products/silicon_solutions/fpgas/easypath/index.htm
> .
> Altera calls it Hardcopy
> http://www.altera.com/products/devices/hardcopyii/hr2-index.jsp
>

Xilinx has NO ASIC solutions. The Easypath is an normal FPGA with less
testing at the fab. may be atually partially faulty. its only tested to
customer bitstream. But the silicon is 1:1 the same as the normal FPGA

antti

There are several smaller companies in the so
called conversion
business using structured ASICs.

google <fpga asic conversion> for 137K hits and more than enough
players

AMI, ViaASIC, Flextronic, and also some surprises in the google list
like Honeywell and epson I had long forgotten about. The active ones
will show up at DAC every year.

For other comments, you could also peek into John Cooleys website, lots
of ASIC, EDA vendor feedback there, some very -ve. When you get
interested in a particular vendor, research them thouroughly.

Since you mentioned cpu porting, I saw on opencores that the OpenRISC
1200 had been ViaASIC ed so I had a look at that, they reduce it down
to a single via mask. They give very little performance info for the
conversion though but suggest that most of the expected speed of full
std cell is obtained, maybe 20% left behind. This core like most
opencores was not planned for FPGA, dates back to the free ASIC IP
hubris. A design planned for BlockRam FPGA should port very well to
these like minded ASICs if only the mask costs can be lowered.

Their kits are 300-500K $ range for HDL in, GDS out for 1 mask. There
have been some poor reviews of this SW, its perhaps still early days.

Not sure how they handle production and quantities, they claim 10x
reduction in FPGA costs which shouldn't be too dificult if you have the
volume.

One thing that seems obvious is project sharing, if ten projects share
1 mask over a full large die, you could probably get 10-20 designs out
of. This is something that maybe the Mosis types should switch too
rather than trying to share all masks per group. But if the 10x
reduction is spread over 10 projects, back to square one.

What I found interesting was their macro block, something like a 1/4
BlockRam of 128 by 32 DP with around 256 logic cells each includes a FF
and handful of gates. I can see right away I would need 2-4 of these
for my cpu and that gives me some useful ASIC info to compare against
FPGA or other full mask flows, long before I spend any time on ASIC
design.

When CA wakes up, somebody from Xilinx will step up to the plate and
trash every other vendor.

John

John,
CA is waking up, but Xilinx does not intend to "trash every other
vendor".

There is room for several approaches, since there are so many
variables:

Up-front NRE cost, time-to-market, general risk, acess to the
leading-edge technology, and reprogrammability all favor FPGAs, and
that's why they are growing faster than the market.
Manufacturing cost per chip, speed, and power consumption favor the
other approaches.

By aggressively using 90 nm technology, and by incorporating larger
functions, our FPGAs have gotten significantly faster and reduced their
power consumption and chip area (FIFO controller, PPC, Ethernet
controller, multiplier/accumulators, SerDes etc.).

There is room for more than one approach, but the prevailing wind is in
favor of the FPGA.
Peter Alfke

Antti,

But "partially faulty" yet 99.999% tested (much better than an ASIC is 
able to be tested) means that any faults which are not being used, don't 
matter.

Every Altera FPGA sold has a redundant column to replace a faulty one. 
So, every one they sell could have a fault.  But it isn't used.  And it 
does not affect reliability (as shown by their product qual tests).

Easypath has also been fully qualified by the reliability testing that 
is required of any device.

Austin

Antti Lukats wrote:

> "Kunal" <k...@gmail.com> schrieb im Newsbeitrag
> news:1...@g49g2000cwa.googlegroups.com...
> 
>>Both Xilinx and Altera has options to move to ASIC-like implementations
>>from FPGA designs. These chips have a lower unit cost.
>>
>>Xilinx calls it EasyPath Solution :
>>http://www.xilinx.com/products/silicon_solutions/fpgas/easypath/index.htm
>>.
>>Altera calls it Hardcopy
>>http://www.altera.com/products/devices/hardcopyii/hr2-index.jsp
>>
> 
> 
> Xilinx has NO ASIC solutions. The Easypath is an normal FPGA with less
> testing at the fab. may be atually partially faulty. its only tested to
> customer bitstream. But the silicon is 1:1 the same as the normal FPGA
> 
> antti
> 
> 
>