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Comp.Arch.FPGA | Signed Multiplication in a Virtex-II Multiplier.
There are 6 messages in this thread.
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Signed Multiplication in a Virtex-II Multiplier. - Anil Khanna - 2003-10-17 18:15:00
I am trying to construct a 6x6 signed multiplier using the Virtex II block multipliers. I know that the V-II multipliers are inherently a 2's complement signed multiplier. However, my question is - by how much should I sign-extend the inputs? Example: Input A - 6 bit Input B - 6 bit Output B- 12 bit Should I connect the remaining ports of the multiplier input (A(7:18)) to A(6) or just A(7:12) to A(6)? The handbook suggests that the sign-extension of the inputs is done till the width of the output. Is this enough or should I do it till the physical width of the multiplier? Thanks Anil______________________________
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Re: Signed Multiplication in a Virtex-II Multiplier. - Peng Cong - 2003-10-18 00:35:00
If you use Xilinx IP Core A - 6 bit B - 6 bit B- 12 bit is enough "Anil Khanna" <a...@mentor.com> 写入消息新闻 :3f906a1c$1...@solnews.wv.mentorg.com... > I am trying to construct a 6x6 signed multiplier using the Virtex II block > multipliers. I know that the V-II multipliers are inherently a 2's > complement signed multiplier. However, my question is - by how much should I > sign-extend the inputs? > > Example: > Input A - 6 bit > Input B - 6 bit > Output B- 12 bit > > Should I connect the remaining ports of the multiplier input (A(7:18)) to > A(6) or just A(7:12) to A(6)? The handbook suggests that the sign-extension > of the inputs is done till the width of the output. Is this enough or should > I do it till the physical width of the multiplier? > > Thanks > > Anil > >
Re: Signed Multiplication in a Virtex-II Multiplier. - Peng Cong - 2003-10-18 00:36:00
If you use Xilinx IP Core A - 6 bit B - 6 bit B- 12 bit is enough "Anil Khanna" <a...@mentor.com> 写入消息新闻 :3f906a1c$1...@solnews.wv.mentorg.com... > I am trying to construct a 6x6 signed multiplier using the Virtex II block > multipliers. I know that the V-II multipliers are inherently a 2's > complement signed multiplier. However, my question is - by how much should I > sign-extend the inputs? > > Example: > Input A - 6 bit > Input B - 6 bit > Output B- 12 bit > > Should I connect the remaining ports of the multiplier input (A(7:18)) to > A(6) or just A(7:12) to A(6)? The handbook suggests that the sign-extension > of the inputs is done till the width of the output. Is this enough or should > I do it till the physical width of the multiplier? > > Thanks > > Anil > >______________________________
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Re: Signed Multiplication in a Virtex-II Multiplier. - Anil Khanna - 2003-10-19 03:34:00
Thanks for the reply. However, I am not using the Xilinx Coregen! Anyways, I figured out the answer to this question and now I have another Q. The handbook claims that there are certain submodules (of the MULT18X18S) available for use. These are submodules like MULT4X4 etc. How does one get access to this and what is the primitive name? Anil "Peng Cong" <p...@sohu.com> wrote in message news:bmqfru$j8h$1...@news.yaako.com... > If you use Xilinx IP Core > A - 6 bit B - 6 bit B- 12 bit > is enough > > "Anil Khanna" <a...@mentor.com> 写入消息新闻 > :3f906a1c$1...@solnews.wv.mentorg.com... > > I am trying to construct a 6x6 signed multiplier using the Virtex II block > > multipliers. I know that the V-II multipliers are inherently a 2's > > complement signed multiplier. However, my question is - by how much should > I > > sign-extend the inputs? > > > > Example: > > Input A - 6 bit > > Input B - 6 bit > > Output B- 12 bit > > > > Should I connect the remaining ports of the multiplier input (A(7:18)) to > > A(6) or just A(7:12) to A(6)? The handbook suggests that the > sign-extension > > of the inputs is done till the width of the output. Is this enough or > should > > I do it till the physical width of the multiplier? > > > > Thanks > > > > Anil > > > > > >
Re: Signed Multiplication in a Virtex-II Multiplier. - Peng Cong - 2003-10-19 21:52:00
Are you sure? I look into the datasheet of Multiplier Generator V6.0, did not see anything about submodules "Anil Khanna" <a...@mentor.com> 写入消息新闻 :3f923e9f$1...@solnews.wv.mentorg.com... > Thanks for the reply. > > However, I am not using the Xilinx Coregen! > Anyways, I figured out the answer to this question and now I have another Q. > > The handbook claims that there are certain submodules (of the MULT18X18S) > available for use. These are submodules like MULT4X4 etc. How does one get > access to this and what is the primitive name? > > Anil > > > "Peng Cong" <p...@sohu.com> wrote in message > news:bmqfru$j8h$1...@news.yaako.com... > > If you use Xilinx IP Core > > A - 6 bit B - 6 bit B- 12 bit > > is enough > > > > "Anil Khanna" <a...@mentor.com> 写入消息新闻 > > :3f906a1c$1...@solnews.wv.mentorg.com... > > > I am trying to construct a 6x6 signed multiplier using the Virtex II > block > > > multipliers. I know that the V-II multipliers are inherently a 2's > > > complement signed multiplier. However, my question is - by how much > should > > I > > > sign-extend the inputs? > > > > > > Example: > > > Input A - 6 bit > > > Input B - 6 bit > > > Output B- 12 bit > > > > > > Should I connect the remaining ports of the multiplier input (A(7:18)) > to > > > A(6) or just A(7:12) to A(6)? The handbook suggests that the > > sign-extension > > > of the inputs is done till the width of the output. Is this enough or > > should > > > I do it till the physical width of the multiplier? > > > > > > Thanks > > > > > > Anil > > > > > > > > > > > >
Re: Signed Multiplication in a Virtex-II Multiplier. - Anil Khanna - 2003-10-22 10:31:00
Look in the handbook. This has more infocompared to the datasheet. "Peng Cong" <p...@sohu.com> wrote in message news:bmvf0o$1o5b$1...@mail.cn99.com... > Are you sure? I look into the datasheet of Multiplier Generator V6.0, > did not see anything about submodules > > "Anil Khanna" <a...@mentor.com> 写入消息新闻 > :3f923e9f$1...@solnews.wv.mentorg.com... > > Thanks for the reply. > > > > However, I am not using the Xilinx Coregen! > > Anyways, I figured out the answer to this question and now I have another > Q. > > > > The handbook claims that there are certain submodules (of the MULT18X18S) > > available for use. These are submodules like MULT4X4 etc. How does one get > > access to this and what is the primitive name? > > > > Anil > > > > > > "Peng Cong" <p...@sohu.com> wrote in message > > news:bmqfru$j8h$1...@news.yaako.com... > > > If you use Xilinx IP Core > > > A - 6 bit B - 6 bit B- 12 bit > > > is enough > > > > > > "Anil Khanna" <a...@mentor.com> 写入消息新闻 > > > :3f906a1c$1...@solnews.wv.mentorg.com... > > > > I am trying to construct a 6x6 signed multiplier using the Virtex II > > block > > > > multipliers. I know that the V-II multipliers are inherently a 2's > > > > complement signed multiplier. However, my question is - by how much > > should > > > I > > > > sign-extend the inputs? > > > > > > > > Example: > > > > Input A - 6 bit > > > > Input B - 6 bit > > > > Output B- 12 bit > > > > > > > > Should I connect the remaining ports of the multiplier input (A(7:18)) > > to > > > > A(6) or just A(7:12) to A(6)? The handbook suggests that the > > > sign-extension > > > > of the inputs is done till the width of the output. Is this enough or > > > should > > > > I do it till the physical width of the multiplier? > > > > > > > > Thanks > > > > > > > > Anil > > > > > > > > > > > > > > > > > > > >