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Comp.Arch.FPGA | ML402 DDR SDRAM
There are 4 messages in this thread.
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ML402 DDR SDRAM - Jered - 2005-11-07 15:11:00
Has anyone been able to get the ML402's DDR SDRAM running with a MIG-generated DDR controller, as opposed to the EDK PLB DDR controller? Xilinx is unable to confirm this works... there's a thread in this group from July with some ML401 MIG questions, but no resolution. My group is interested in using the 402 in a non-SoC application, so we're sort of wondering if MIG has been proven here. Thanks!
Re: ML402 DDR SDRAM - 2005-11-08 04:36:00
Hi, Jered, I tried months before to use MIG007 generating a DDR controller for ML310, failed and the xilinx support did not help to get through. I modified everything to fit ml310 kit and when I download the generated testbench, nothing happened in the DDR. You can discuss with me by: xjf77(at)yahoo.com. regards
Re: ML402 DDR SDRAM - Jihoon - 2005-12-07 12:24:00
>Hi, Jered, I tried months before to use MIG007 generating a DDR controllerfor ML310, failed and the xilinx support did not help to get through. Imodified everything to fit ml310 kit and when I download the generatedtestbench, nothing happened in the DDR. You can discuss with me by:xjf77(at)yahoo.com. regards > I am running MIG DDR rel6 on the ML310. You need to work around to connect rst_dqs_div_in and rst_dqs_div_outoutside of FPGA.
Re: ML402 DDR SDRAM - Jihoon - 2005-12-07 12:24:00
>Hi, Jered, I tried months before to use MIG007 generating a DDR controllerfor ML310, failed and the xilinx support did not help to get through. Imodified everything to fit ml310 kit and when I download the generatedtestbench, nothing happened in the DDR. You can discuss with me by:xjf77(at)yahoo.com. regards > Hi, all, I forgot to tell you guys something. MIG DDR support only unbuffered DIMMas far as I know. The DIMM coming with ML310 is buffered DIMM. In my case,I replaced DIMM and it works fine.______________________________
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