Hi,
I am having problems with XST Synthesis from Xilinx. When synthesizing
a unit from my created IP, the synthesis tool just stops, providing no
error explanation. The last messages I get from the log files are the
following:
Synthesizing Unit <DEV4_uid101>.
    Related source file is
//hamurabi.iro.umontreal.ca/brassaro/projet/Systeme_Test/pcores/pow_function_v1_00_a/hdl/v
hdl/DEV4_uid101.vhd.
WARNING:Xst:647 - Input <u_sid88_sid1909_sid77_uid2807<0>> is never
used.
WARNING:Xst:647 - Input <u_sid79_sid1921_sid88_uid2830<0>> is never
used.
WARNING:Xst:647 - Input <u_sid88_sid1819_sid64_uid3043<0>> is never
used.
WARNING:Xst:647 - Input <u_sid88_sid1847_sid68_uid2759<0>> is never
used.
WARNING:Xst:647 - Input <u_sid88_sid1875_sid72_uid2981<0>> is never
used.
WARNING:Xst:647 - Input <u_sid88_sid76_sid1903_uid3116<0>> is never
used.
WARNING:Xst:647 - Input <u_sid88_sid78_sid1915_uid2953<0>> is never
used.
WARNING:Xst:647 - Input <u_sid1825_sid88_sid65_uid2806<0>> is never
used.
WARNING:Xst:647 - Input <u_sid88_sid73_sid1881_uid2924<0>> is never
used.
WARNING:Xst:647 - Input <u_sid71_sid88_sid1869_uid3130<0>> is never
used.
    Found finite state machine <FSM_0> for signal
<S208_sid107_sid102_sid106_sid135_sid113_sid131_uid2900>.

-----------------------------------------------------------------------
    | States             | 12
  |
    | Transitions        | 25
  |
    | Inputs             | 13
  |
    | Outputs            | 12
  |
    | Clock              | u_sid95_sid88_sid98_uid2705 (rising_edge)
   |
    | Clock enable       |
S122_sid103_sid2164_sid2166_sid102_sid2167_uid2961 (positive)       |
    | Power Up State     | fsl_interface_start
  |
    | Encoding           | automatic
  |
    | Implementation     | automatic
  |

-----------------------------------------------------------------------

Please help!!!
Thank you

Forgot to mention that i am using EDK 6.3i.

<b...@iro.umontreal.ca> wrote in message 
news:1...@o13g2000cwo.googlegroups.com...
> Forgot to mention that i am using EDK 6.3i.
>

Check the synthesis report for details, if you have not already done so. 
Sometimes errors don't appear inthe dialog but in the report for which there 
are various in ISE. Also, check to see if your connections are complete, 
perhaps none are recognized. If all fails try opening a web support issue 
with Xilinx. This can take time but the response often hits the heart ofthe 
problem.

-Andrew 

I checked the reports, and no other info except
the one I posted is
given. What bothers me also is that synthesis works on altera tools,
like Quartus II. Could it be an error that Quartus does not find in the
design, or is it a bug in Xilinx tools?

Found a way to synthesize... Set the fsm_extract
flag to false. Seems
like FSM extraction does not work for my design!