Hi,Does somebody know DCM corner issues?  My DCM is not running at veryhigh clock rate (only 107MHz), so I don't think this issue isconnected with XAPP685 application notes(http://direct.xilinx.com/bvdocs/appnotes/xapp685.pdf)This DCM is used with an DDR-SDRAM memory controller, and when I placeit at X3Y0 instead of X2Y0, memory reading often fails (data arewrong).    Thus the solution is not complicated, I just need not touse DCM X3Y0 but I would like to understand why it fails and ifsomebodyelse knows this problem.    Thank you.

Cher Sebastien,
What part are you using? Virtex4? Have you seen answer 21127?
HTH, Syms.

"seb_tech_fr" <s...@techway-dot-fr.no-spam.invalid> wrote in
message news:G...@giganews.com...
> Hi,
> Does somebody know DCM corner issues?  My DCM is not running at very
> high clock rate (only 107MHz), so I don't think this issue is
> connected with XAPP685 application notes

21127 would not cause what Sebastien is
experiencing (on  V4),

That concerns itself with a lower than 500 MHz possible CLKIN if the 
device has been baked at high Vdd AND high temperature (see the NBTI 
white paper).

In actual fact, we saw this effect in HTOL testing with the production 
tester, but have never seen it in actual fact either on the test bench, 
or in any testing done by any customers.

There is a suspicion that the testing done is far too tough, and the 
problem only appears on the production tester (which tests to >700 MHz, 
with a +/- 100 MHz sampling) in its tests to ensure that the DCM will 
operate over all corners of the process, voltage and temperatures).


For any device with a DCM:

More likely is that the placement of the DCM affects the timing of the 
paths that are used.

Check all the constraints, and check to see that the global clock 
resources are bring routed properly by looking at the design in FPGA Editor.

For V2 Pro there are clock macros which are used to minimize the 
possible skew from different DCM locations.  If this is V2 Pro, then I 
could see this happening if the macros were not being used.

Austin



Symon wrote:

> Cher Sebastien,
> What part are you using? Virtex4? Have you seen answer 21127?
> HTH, Syms.
> 
> "seb_tech_fr" <s...@techway-dot-fr.no-spam.invalid> wrote
in
> message news:G...@giganews.com...
> 
>>Hi,
>>Does somebody know DCM corner issues?  My DCM is not running at very
>>high clock rate (only 107MHz), so I don't think this issue is
>>connected with XAPP685 application notes
> 
> 
> 

Hi Austin,I use an V2P70, which is loaded at 76%.I don't use any macro for DCM. Which one should I use?Concerning placement and routing, all constraints have been met. It'spossible that this part is not constraint enough...Additional information. When I use a lighter version of my design(which is loaded at 20%), it works..> Austin Leseawrote:21127 would not cause what Sebastien is experiencing (on  V4),> > That concerns itself with a lower than 500 MHz possible CLKIN if the> device has been baked at high Vdd AND high temperature (see the NBTI> white paper).> > In actual fact, we saw this effect in HTOL testing with theproduction > tester, but have never seen it in actual fact either on the testbench, > or in any testing done by any customers.> > There is a suspicion that the testing done is far too tough, and the> problem only appears on the production tester (which tests to>700 MHz, > with a +/- 100 MHz sampling) in its tests to ensure that the DCMwill > operate over all corners of the process, voltage and temperatures).> > > For any device with a DCM:> > More likely is that the placement of the DCM affects the timing ofthe > paths that are used.> > Check all the constraints, and check to see that the global clock > resources are bring routed properly by looking at the design in FPGAEditor.> > For V2 Pro there are clock macros which are used to minimize the > possible skew from different DCM locations.  If this is V2 Pro, thenI > could see this happening if the macros were not being used.> > Austin> > > > Symon wrote:> > Cher Sebastien,> What part are you using? Virtex4? Have you seen answer 21127?> HTH, Syms.> > "seb_tech_fr"<s...@techway-dot-fr.no-spam.invalid> wrote in> message news:G...@giganews.com...> > Hi,> Does somebody know DCM corner issues?  My DCM is not running atvery> high clock rate (only 107MHz), so I don't think this issue is> connected with XAPP685 application notes> > > [/quote:e23a8545fa]

http://www.xilinx.com/bvdocs/appnotes/xapp685.pdf

See page 2.

Austin

seb_tech_fr wrote:
> Hi Austin,
> I use an V2P70, which is loaded at 76%.
> I don't use any macro for DCM. Which one should I use?
> 
> Concerning placement and routing, all constraints have been met. It's
> possible that this part is not constraint enough...
> 
> Additional information. When I use a lighter version of my design
> (which is loaded at 20%), it works..
> 
> 
>>Austin Leseawrote:
> 
> 21127 would not cause what Sebastien is experiencing (on  V4),
> 
>>That concerns itself with a lower than 500 MHz possible CLKIN if the
> 
> 
>>device has been baked at high Vdd AND high temperature (see the NBTI
> 
> 
>>white paper).
>>
>>In actual fact, we saw this effect in HTOL testing with the
> 
> production 
> 
>>tester, but have never seen it in actual fact either on the test
> 
> bench, 
> 
>>or in any testing done by any customers.
>>
>>There is a suspicion that the testing done is far too tough, and the
> 
> 
>>problem only appears on the production tester (which tests to
>>700 MHz, 
>>with a +/- 100 MHz sampling) in its tests to ensure that the DCM
> 
> will 
> 
>>operate over all corners of the process, voltage and temperatures).
>>
>>
>>For any device with a DCM:
>>
>>More likely is that the placement of the DCM affects the timing of
> 
> the 
> 
>>paths that are used.
>>
>>Check all the constraints, and check to see that the global clock 
>>resources are bring routed properly by looking at the design in FPGA
> 
> Editor.
> 
>>For V2 Pro there are clock macros which are used to minimize the 
>>possible skew from different DCM locations.  If this is V2 Pro, then
> 
> I 
> 
>>could see this happening if the macros were not being used.
>>
>>Austin
>>
>>
>>
>>Symon wrote:
>>
>>Cher Sebastien,
>>What part are you using? Virtex4? Have you seen answer 21127?
>>HTH, Syms.
>>
>>"seb_tech_fr"
> 
> <s...@techway-dot-fr.no-spam.invalid> wrote in
> 
>>message news:G...@giganews.com...
>>
>>Hi,
>>Does somebody know DCM corner issues?  My DCM is not running at
> 
> very
> 
>>high clock rate (only 107MHz), so I don't think this issue is
>>connected with XAPP685 application notes
>>
>>
>>[/quote:e23a8545fa]
> 
> 

Thank you Austin.I have to try, but the application note depicts exactly my case.> Austin Leseawrote:http://www.xilinx.com/bvdocs/appnotes/xapp685.pdf>; > See page 2.> > Austin> > seb_tech_fr wrote:> Hi Austin,> I use an V2P70, which is loaded at 76%.> I don't use any macro for DCM. Which one should I use?> > Concerning placement and routing, all constraints have been met.It's> possible that this part is not constraint enough...> > Additional information. When I use a lighter version of my design> (which is loaded at 20%), it works..> > > Austin Leseawrote:> > 21127 would not cause what Sebastien is experiencing (on  V4),> > That concerns itself with a lower than 500 MHz possible CLKIN ifthe> > > device has been baked at high Vdd AND high temperature (see theNBTI> > > white paper).> > In actual fact, we saw this effect in HTOL testing with the> > production> > tester, but have never seen it in actual fact either on the test> > bench,> > or in any testing done by any customers.> > There is a suspicion that the testing done is far too tough, andthe> > > problem only appears on the production tester (which tests to> 700 MHz,> with a +/- 100 MHz sampling) in its tests to ensure that the DCM> > will> > operate over all corners of the process, voltage and temperatures).> > > For any device with a DCM:> > More likely is that the placement of the DCM affects the timing of> > the> > paths that are used.> > Check all the constraints, and check to see that the global clock> resources are bring routed properly by looking at the design inFPGA> > Editor.> > For V2 Pro there are clock macros which are used to minimize the> possible skew from different DCM locations.  If this is V2 Pro,then> > I> > could see this happening if the macros were not being used.> > Austin> > > > Symon wrote:> > Cher Sebastien,> What part are you using? Virtex4? Have you seen answer 21127?> HTH, Syms.> > "seb_tech_fr"> > s...@techway-dot-fr.no-spam.invalid> wrote in> > message news:G...@giganews.com...> > Hi,> Does somebody know DCM corner issues?  My DCM is not running at> > very> > high clock rate (only 107MHz), so I don't think this issue is> connected with XAPP685 application notes> > > [/quote:2c5a58d0bc][/quote:2c5a58d0bc]