Hi,

in my design I would like to have the possibility to switch beetween
two
clock signals: 'clk' (this is my main clock) and 'ext_clk' (the second,

external clock) and the output clock is 'clk_out'. It all depends on
one
signal - let's call it 'temp'. 'Clk_out' is then used in the
sensitivity
list of some process ("process(clk_out) ..."). But when I code it in
VHDL
like this:

clk_out <= clk when temp = '0' else ext_clk;

in ISE I get the message that clk_out signal
"is generated by combinatorial logic and XST is not able to identify
which
are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify te clock signal(s)
generated by combinatorial logic.
Some clock signals were not autmatically buffered by XST with BUFG/BUFR

resources. Please use the buffer_type constraint in order to insert
these
buffers to the clock signals to help prevent skew problems."

So how should I solve this problem correctly?

Thanks in advance,
Tomek

Go to the Xilinx website   xilinx.com
Enter    six easy pieces   in the search window
Open the TechXclusive article with that title
Scroll down to #6

and you find a circuit that allows you to switch between two unrelated
clock frequencies, and do the switching asynchronously to either clock.

The only limitation is that both clocks must be free-running, since you
cannot switch away from a locked-up clock.

Peter Alfke. Xilinx Applications

You can also use this insanely unwieldly URL:

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See below
rybol wrote:
> Hi,
> 
> in my design I would like to have the possibility to switch beetween
> two
> clock signals: 'clk' (this is my main clock) and 'ext_clk' (the second,
> 
> external clock) and the output clock is 'clk_out'. It all depends on
> one
> signal - let's call it 'temp'. 'Clk_out' is then used in the
> sensitivity
> list of some process ("process(clk_out) ..."). But when I code it in
> VHDL
> like this:
> 
> clk_out <= clk when temp = '0' else ext_clk;
> 
> in ISE I get the message that clk_out signal
> "is generated by combinatorial logic and XST is not able to identify
> which
> are the primary clock signals.
> Please use the CLOCK_SIGNAL constraint to specify te clock signal(s)
> generated by combinatorial logic.
> Some clock signals were not autmatically buffered by XST with BUFG/BUFR
> 
> resources. Please use the buffer_type constraint in order to insert
> these
> buffers to the clock signals to help prevent skew problems."
> 
> So how should I solve this problem correctly?
> 
> Thanks in advance,
> Tomek
> 

intantiate a BUFGMUX (from ISE tepmlates)

Library UNISIM;
use UNISIM.vcomponents.all;

    -- BUFGMUX_VIRTEX4: Global Clock Buffer 2-to-1 MUX
    --                  Virtex-4
    -- Xilinx HDL Language Template version 8.1i

    BUFGMUX_VIRTEX4_inst : BUFGMUX_VIRTEX4
    generic map (
       INIT_OUT => 0,         -- Inital value of 0 or 1 after configuration
       PRESELECT_I0 => FALSE, -- TRUE/FALSE set the I0 input after 
configuration
       PRESELECT_I1 => FALSE) -- TRUE/FALSE set the I1 input after 
configuration
    port map (
       O => O,    -- Clock MUX output
       I0 => I0,  -- Clock0 input
       I1 => I1,  -- Clock1 input
       S => S     -- Clock select input
    );

    -- End of BUFGMUX_VIRTEX4_inst instantiation

Regards,
Aurash

http://www.xilinx.com/xcell/xl37/xcell37_54.pdf

http://www.xilinx.com/xcell/xl37/xcell37_54.pdf