I have a DSP chip with address/data bus and
control pins interfaced to a
Spartan IIE.
The DSP is driving these lines, but I do not ever need to use some of them
in my FPGA design.
What should be done with these input pins?  At the moment they are
completely unassigned (using Webpack).  Some are strobing or clocking, and
others just fixed value.

Also, I have assigned two pins which connect to ground on the DSP board as
GROUND_OUT <= '0';
Is this adequate for grounding?  I guess there is no such thing as a ground
'input' on an FPGA as you cannot assign an input to '0'.

The DSP bus is driven out through a TI CMOS transceiver/buffer chip (on TI
C6711 DSK board) and I have connected this bus directly to inputs on the
FPGA, configured as LVTTL as logic 1 is 3.3V.  Is this OK?  Do I need to use
pullup or pulldown "virtual" resistors on the FPGA inputs?

Many thanks for your help

Tom

Hi Tom

You should find that any pins declared as inputs but unused in your design
will be optimised out by the Xilinx tools during synthesis and mapping.
Once you've placed and routed your design, right click on the "Generate
Programming File" process and choose "Properties", select the
"Configuration
Options" tab and choose "Float" for unused IOB pins.  This will ensure
that
all unused pins are tristated.  That way even if the DSP does drive them, no
contention can occur.

I'm not quite sure what you mean by "adequate grounding".  You can assign IO
pins as outputs and tie them to GND to improve the chip's grounding.
However, as long as all the dedicated GND pins are connected, this shouldn't
really be necessary.

I'm not sure what levels the CMOS transceiver works at.  As long as it is
3V3 TTL compatible you should be fine with your setup as is.

Hope this helps

Sam

"Tom Derham" <t...@NOSPAM.ee.ucl.ac.uk> wrote in message
news:bnjn2a$oo4$1...@uns-a.ucl.ac.uk...
> I have a DSP chip with address/data bus and control pins interfaced to a
> Spartan IIE.
> The DSP is driving these lines, but I do not ever need to use some of them
> in my FPGA design.
> What should be done with these input pins?  At the moment they are
> completely unassigned (using Webpack).  Some are strobing or clocking, and
> others just fixed value.
>
> Also, I have assigned two pins which connect to ground on the DSP board as
> GROUND_OUT <= '0';
> Is this adequate for grounding?  I guess there is no such thing as a
ground
> 'input' on an FPGA as you cannot assign an input to '0'.
>
> The DSP bus is driven out through a TI CMOS transceiver/buffer chip (on TI
> C6711 DSK board) and I have connected this bus directly to inputs on the
> FPGA, configured as LVTTL as logic 1 is 3.3V.  Is this OK?  Do I need to
use
> pullup or pulldown "virtual" resistors on the FPGA inputs?
>
> Many thanks for your help
>
> Tom
>
>