Hi All,

I want some guidence for encoding schemes used in ethernet

I know that for gigabit ethernet mostly the 8b10b encoding scheme is
used
and also I have heard about 64b/66b scheme.

which one is actually used....?

If I need to send my data on ethernet which one I should use and while
receiving any data, is there any method for detecting that the
receiving data is coded in which scheme...?

Thanks & Regards 
Kedar

Hi,

The encoding is handled by the PHY. Are you implementing the PHY on an
Fpga?

Alan

Hi,

The encoding is handled by the PHY. Are you implementing the PHY on an
Fpga?

Alan

Why don't you use a Gigabit PHY (for example
Marvell 88E1111) ?
Then you only have to care about the interface FPGA <--> PHY.

Rgds
Andr=E9

yes I am trying to look at if I can implement an
ethernet multiplexer
in FPGA

if you have any info please forward it to me.

thanks & regards
Kedar

k...@gmail.com wrote:
> Hi All,
> 
> I want some guidence for encoding schemes used in ethernet
> 
> I know that for gigabit ethernet mostly the 8b10b encoding scheme is
> used
> and also I have heard about 64b/66b scheme.
> 
> which one is actually used....?
8b/10b is used for Gigabit Ethernet, 64b/66b for 10-Gigabit-Ethernet.
Both encoding schemes are not only used for Ethernet, but for all sorts
of high-speed serial interfaces, like Fibre Channel and the like.

Obviously, the overhead is much less for 64b/66b (3% compared to 20%),
but it's more "complicated" to implement, so you have to find the
trade-off there. 8b/10b is usually done with a simple look-up-table,
some sort of memory that holds all the possible encoded values. For
64b/66b this table would be too big, so there's ways to do the encoding
in logic, like in this appnote:

http://direct.xilinx.com/bvdocs/appnotes/xapp687.pdf

> If I need to send my data on ethernet which one I should use and while
> receiving any data, is there any method for detecting that the
> receiving data is coded in which scheme...?
Usually, the encoding is done in a PHY, not in the FPGA-logic. Normally
you would implement the Ethernet MAC inside the FPGA and then use one of
the MII-interfaces or maybe XAUI to connect it to an external PHY, who
does the encoding and the actual transmission over copper or fiber cables.

Now it depends on what kind of FPGA you're using. Virtex II Pro and
Virtex 4 FX (except the smallest parts) have RocketIOs embedded that
have units für 8b/10b ("normal" RocketIO) or 64b/66b (RocketIO-X) en-
and decoding, so you don't need to do anything there anyway. Virtex 4 FX
also have ready-to-use Ethernet MACs built in, so you don't even have to
implement that.

You need the PHY anyway, be it inside the FPGA or as an external
component, so normally I'd say there's no need to worry about the
encoding schemes because you have some other component that handles it.

cu,
Sean

Hi All,

Thanks a lot for your replies.
Actually speaking I am trying to implement ethernet multiplexer or
switch.
the switch will have far more intelligence than mux, so my first step
would be to try and implement a mux using the FPGA series which has a
rocket IO support as Sean has said in the reply.
the decision of using PHY ext. or internal to FPGA (implemented by
Xilinx or Altera what ever I target to) will depend on various things.

But right now I am in study phase of how to implement a Ethernet switch
or Mux  in an FPGA.

so one more Q for all Superiors

1. Do I need a MAC for every input terminal of a mux or switch.



Thank you very much for your replies .
please keep posting your valuable helps I will need that a lot.

Thanks & Regards,
Kedar