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Comp.Arch.FPGA | FPGA -> ASIC`

There are 5 messages in this thread.

You are currently looking at messages 0 to 5.

FPGA -> ASIC` - Eli Hughes - 2006-01-06 10:12:00

Hello:

I have absolutely no experience in ASIC design.  I do however have 
experience in FPGA.  I have a CPU design that is currently working in a 
Xilinx FPGA.  The design fits in a spartan3 XCS200 (144pin Package).

I want to migrate to a fully custom chip in a different package.  My 
design only has 10 pins that are used for signals so I want to get into 
a very small package such as a SOIC20 or a micro lead frame (QFN) 32 
package.


Is it possible to take a synthesizable netlist to an ASIC vendor and get 
a custom chip in a custom package?  What kind of Costs should I expect? 
   Right now the FPGA solution is too big and to expensive for the runs 
I need.  The Spartan chips need to get to around $4 (and in a smaller 
package) to become cost effective (rather than $20).  Also, I want to 
get rid of the configuration FLASH to save $$ (Hence the ASIC)

Thanks,
Eli



Re: FPGA -> ASIC` - Antti Lukats - 2006-01-06 10:25:00

"Eli Hughes" <e...@psu.edu>
schrieb im Newsbeitrag 
news:dpm1ca$1kqc$1...@f04n12.cac.psu.edu...
> Hello:
>
> I have absolutely no experience in ASIC design.  I do however have 
> experience in FPGA.  I have a CPU design that is currently working in a 
> Xilinx FPGA.  The design fits in a spartan3 XCS200 (144pin Package).
>
> I want to migrate to a fully custom chip in a different package.  My 
> design only has 10 pins that are used for signals so I want to get into a 
> very small package such as a SOIC20 or a micro lead frame (QFN) 32 
> package.
>
>
> Is it possible to take a synthesizable netlist to an ASIC vendor and get a 
> custom chip in a custom package?  What kind of Costs should I expect? 
> Right now the FPGA solution is too big and to expensive for the runs I 
> need.  The Spartan chips need to get to around $4 (and in a smaller 
> package) to become cost effective (rather than $20).  Also, I want to get 
> rid of the configuration FLASH to save $$ (Hence the ASIC)
>
> Thanks,
> Eli

Xilinx chips can go as low as $4, but well depends on quantity and the 
config flash is a pain

but check also Actel PA3 in CSP package offering, the package is just a bit 
larger than QFN32, but I think the PCB estate a little smaller than SOIC20 - 
well cost can be too high, Lattice doesnt have QFN so far, only BGA what is 
possible too big for you

www.chipx.com has qfn56 as smallest package

antti 



Re: FPGA -> ASIC` - DerekSimmons@FrontierNet.net - 2006-01-06 10:30:00

Have you looked at Altera's HardCopy device? It
allows you to migrate a
FPGA (Startix/Cyclone) design to a HardCopy device. It is suppose to
have some of the advantages of ASIC device (price was one of them).

Derek

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Re: FPGA -> ASIC` - Jim Granville - 2006-01-07 16:54:00

Eli Hughes wrote:
> Hello:
> 
> I have absolutely no experience in ASIC design.  I do however have 
> experience in FPGA.  I have a CPU design that is currently working in a 
> Xilinx FPGA.  The design fits in a spartan3 XCS200 (144pin Package).
> 
> I want to migrate to a fully custom chip in a different package.  My 
> design only has 10 pins that are used for signals so I want to get into 
> a very small package such as a SOIC20 or a micro lead frame (QFN) 32 
> package.
> 
> 
> Is it possible to take a synthesizable netlist to an ASIC vendor and get 
> a custom chip in a custom package?  What kind of Costs should I expect? 
>   Right now the FPGA solution is too big and to expensive for the runs I 
> need.  The Spartan chips need to get to around $4 (and in a smaller 
> package) to become cost effective (rather than $20).  Also, I want to 
> get rid of the configuration FLASH to save $$ (Hence the ASIC)

  You do not mention your volumes : ASICs (and even some FPGA-ASIC 
alternatives, as well ) have substantial NRE (setup) costs, as
well as minimum volumes.
  FPGA vendors boast about sub $3 'future-price' devices, and also
have flows that lower prices for stable code and high volume.
- but their high volume, and your high volume, may be different :)
  For cheapest config, look at SPI FLASH devices.

-jg


Re: FPGA -> ASIC` - H. Peter Anvin - 2006-01-12 01:33:00

D...@FrontierNet.net wrote:
> Have you looked at Altera's HardCopy device? It allows you to migrate a
> FPGA (Startix/Cyclone) design to a HardCopy device. It is suppose to
> have some of the advantages of ASIC device (price was one of them).

Stratix/Stratix II, rather.  The HardCopy devices are definitely high 
end.  Definitely seems like a nice migration program, though.

	-hpa