Sign in

username:

password:



Not a member?

Search Comp.Arch.FPGA



Search tips

fpga by Keywords

Altera | ASIC | CPLD | Cyclone | DCM | DDR | DSP | Ethernet | ISE | JTAG | Linux | LVDS | Microblaze | ML310 | Modelsim | NIOS | OPB | PCI | Quartus | RocketIO | SDRAM | Spartan | Spartan3 | SRAM | Stratix | Verilog | VHDL | Virtex | Virtex-4 | Virtex-II | Xilinx | XST

Ads

See Also

DSPEmbedded SystemsElectronics

Comp.Arch.FPGA | Starting with LVDS

There are 15 messages in this thread.

You are currently looking at messages 10 to 15.

Re: Starting with LVDS - Frank Schreiber - 2006-01-23 04:17:00

So,
in this case should I provide 8 bits for data, and 1 bits for clock ?
Any clock else ?
Frank
>
>
> think of LVDS that you use 2 wires an not 1 for 1 signal
>
> for LVDS its irrelevant if the signal is clock or data or whatever
>
> what I said is that if you have DAC chip that uses LVDS standard then this
> DAC chip does need a LVDS clock to latch the data, but its only my guess,
> you really did not provide enough info.
>
>
> --
> Antti Lukats
> http://www.xilant.com
>
>


______________________________
Join the blogging team on FPGARelated.com and earn rewards! Details Here.



Re: Starting with LVDS - Antti Lukats - 2006-01-23 04:22:00

"Frank Schreiber"
<f...@googlemail.com> schrieb im Newsbeitrag 
news:dr26uq$n0i$1...@anderson.hrz.tu-chemnitz.de...
> So,
> in this case should I provide 8 bits for data, and 1 bits for clock ?
> Any clock else ?
> Frank
>>

if you have a DAC chip with 8 bit DDR LVDS then you have 8 bit data in FPGA 
and 1 bit clock, and there will be 16 actual data wires(8 +- pairs)) from 
FPGA and 2 clock lines (1 +- pair)

but you can not expect to get help if you dont say what is the thing that is 
connnected to FPGA, I assume its an high speed digital analog converter, but 
only you know it for sure, others can only guess

-- 
Antti Lukats
http://www.xilant.com 


______________________________
Join the blogging team on FPGARelated.com and earn rewards! Details Here.

Re: Starting with LVDS - Symon - 2006-01-23 05:04:00

Frank,
From your IP address I guess you're a Physics student at university. I'd 
suggest you go down the corridor to the EE department and ask someone there 
who will be able to help you face to face. Even if they can't answer your 
question, they could probably tell you what to post here to get an answer.
HTH and good luck, Syms.
"Frank Schreiber" <f...@googlemail.com> wrote in message 
news:dr0fec$kvu$1...@anderson.hrz.tu-chemnitz.de...
> Dear all
> I'm starting with LVDS.
> My task is sending 8-bits signal to LVDS Transmitter port on my board.
> I declared a 8 bits vector, assigned pins, and changed values in 8-bits
> signal, but nothing happended in my oscilloscope. Assume that pins-out are
> right assigned, all wires and DAC are working perfectly.
> Can anyone advise me, how to make it works.
> Many thanks
> Frank
>
> 



Re: Starting with LVDS - Rob - 2006-01-23 16:38:00

Are you trying to implement the transmitter
within the FPGA?

"Frank Schreiber" <f...@googlemail.com> wrote in message 
news:dr0fec$kvu$1...@anderson.hrz.tu-chemnitz.de...
> Dear all
> I'm starting with LVDS.
> My task is sending 8-bits signal to LVDS Transmitter port on my board.
> I declared a 8 bits vector, assigned pins, and changed values in 8-bits
> signal, but nothing happended in my oscilloscope. Assume that pins-out are
> right assigned, all wires and DAC are working perfectly.
> Can anyone advise me, how to make it works.
> Many thanks
> Frank
>
> 



Re: Starting with LVDS - Philip Freidin - 2006-01-24 21:13:00

On Mon, 23 Jan 2006 09:43:02 +0100, "Frank
Schreiber" <f...@googlemail.com> wrote:
>Dear all,
>I am using Virtex 4 from Xillinx, and I really missed the clock for LVDS.
>So, should I transfer data to LVDS each time posedge of the clock.
>The clock should be LVDS clock, LTTL clock or any clock is possible.
>Many thanks
>Frank

I don't understand you Frank! Multiple times others have
explained to you that if you don't give sufficient information,
it is IMPOSSIBLE to answer your questions.

Give the following information, and maybe you can be helped:

1) Which exact Xilinx part number are you using.

2) What EXACT device (part number) are you connecting it to

3) How many wires total have you connected between these chips,
   (LVDS should be 2 wires per signal, 8 data + clock would total
    to 18 wires)

4) Bonus info would be the manufacturer of the board (or if it
   is your own design, some more details of the design and the
   purpose), the clock rate you are trying to use, whether the
   data is single or double data rate.



Philip Freidin
Fliptronics

previous | 1 | 2