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Comp.Arch.FPGA | Multichannel Opb Memory Controller question
There are 10 messages in this thread.
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Multichannel Opb Memory Controller question - Marco T. - 2006-01-27 04:42:00
Hallo, I would develop a system based on opb multichannel memory sdram controller. I would connect Microblaze to the controller using xcl and not opb bus. I would also connect an external microcontroller to sdram: I thought to create a custom opb master peripheral and connect it to opb bus. The opb bus will have a master (the external micro) and a slave (the sdram). Is it reliable? When I access memory from the external micro, may I use the address generated using EDK Platform Studio? In this way I should have the memory controller mapped in example at 0X22000000. May I use this address to gain access from microblaze and the external microcontroller? Many Thanks Marco______________________________
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Re: Multichannel Opb Memory Controller question - Antti Lukats - 2006-01-27 04:45:00
>Marco T." <m...@blabla.com> schrieb im Newsbeitrag >news:drcptn$ueq$1...@nnrp.ngi.it... > Hallo, > I would develop a system based on opb multichannel memory sdram > controller. > > I would connect Microblaze to the controller using xcl and not opb bus. > > I would also connect an external microcontroller to sdram: I thought to > create a custom opb master peripheral and connect it to opb bus. > > The opb bus will have a master (the external micro) and a slave (the > sdram). > > Is it reliable? > > When I access memory from the external micro, may I use the address > generated using EDK Platform Studio? > > In this way I should have the memory controller mapped in example at > 0X22000000. > > May I use this address to gain access from microblaze and the external > microcontroller? > > Many Thanks > Marco > whatever you connect to OPB bus can not have access to memory on XCL as cachelink FSL bus is accessible only from MicroBlaze, not from busses connected to MB -- Antti Lukats http://www.xilant.com
Re: Multichannel Opb Memory Controller question - Marco T. - 2006-01-27 04:55:00
"Antti Lukats" <a...@openchip.org> wrote in message news:drcq39$imr$00$1...@news.t-online.com... > >Marco T." <m...@blabla.com> schrieb im Newsbeitrag > >news:drcptn$ueq$1...@nnrp.ngi.it... >> Hallo, >> I would develop a system based on opb multichannel memory sdram >> controller. >> >> I would connect Microblaze to the controller using xcl and not opb bus. >> >> I would also connect an external microcontroller to sdram: I thought to >> create a custom opb master peripheral and connect it to opb bus. >> >> The opb bus will have a master (the external micro) and a slave (the >> sdram). >> >> Is it reliable? >> >> When I access memory from the external micro, may I use the address >> generated using EDK Platform Studio? >> >> In this way I should have the memory controller mapped in example at >> 0X22000000. >> >> May I use this address to gain access from microblaze and the external >> microcontroller? >> >> Many Thanks >> Marco >> > whatever you connect to OPB bus can not have access to memory on XCL > as cachelink FSL bus is accessible only from MicroBlaze, not from busses > connected to MB > > -- > Antti Lukats > http://www.xilant.com > As usual, my english is terrible... I'm sorry! I try to be more clear. Microblaze will access sdram through XCL. Microblaze will NOT be connected to opb bus. An external micro will access sdram through OPB bus. It will be a master, the only master of the opb bus. The memory controller will be the only slave of opb bus. Is it reliable? Can Microblaze write a region of sdram and "simultaneously" external micro read another region? Sorry again! Marco
Re: Multichannel Opb Memory Controller question - Antti Lukats - 2006-01-27 04:58:00
"Marco T." <m...@blabla.com> schrieb im Newsbeitrag news:drcqlq$um5$1...@nnrp.ngi.it... > > "Antti Lukats" <a...@openchip.org> wrote in message > news:drcq39$imr$00$1...@news.t-online.com... >> >Marco T." <m...@blabla.com> schrieb im Newsbeitrag >> >news:drcptn$ueq$1...@nnrp.ngi.it... >>> Hallo, >>> I would develop a system based on opb multichannel memory sdram >>> controller. >>> >>> I would connect Microblaze to the controller using xcl and not opb bus. >>> >>> I would also connect an external microcontroller to sdram: I thought to >>> create a custom opb master peripheral and connect it to opb bus. >>> >>> The opb bus will have a master (the external micro) and a slave (the >>> sdram). >>> >>> Is it reliable? >>> >>> When I access memory from the external micro, may I use the address >>> generated using EDK Platform Studio? >>> >>> In this way I should have the memory controller mapped in example at >>> 0X22000000. >>> >>> May I use this address to gain access from microblaze and the external >>> microcontroller? >>> >>> Many Thanks >>> Marco >>> >> whatever you connect to OPB bus can not have access to memory on XCL >> as cachelink FSL bus is accessible only from MicroBlaze, not from busses >> connected to MB >> >> -- >> Antti Lukats >> http://www.xilant.com >> > > As usual, my english is terrible... I'm sorry! I try to be more clear. > > Microblaze will access sdram through XCL. Microblaze will NOT be connected > to opb bus. > > An external micro will access sdram through OPB bus. It will be a master, > the only master of the opb bus. The memory controller will be the only > slave of opb bus. > > Is it reliable? > > Can Microblaze write a region of sdram and "simultaneously" external micro > read another region? > > Sorry again! > > Marco > almost anything can be made reliable, but what you are suggesting is not REASONABLE. if SDRAM is on XCL then whatever external micro should access the SDRAM controller that does arbitration directly - using OPB here is not a good idea. Antti
Re: Multichannel Opb Memory Controller question - Marco T. - 2006-01-27 05:07:00
"Antti Lukats" <a...@openchip.org> wrote in message news:drcqsu$2rq$02$1...@news.t-online.com... > "Marco T." <m...@blabla.com> schrieb im Newsbeitrag > news:drcqlq$um5$1...@nnrp.ngi.it... >> >> "Antti Lukats" <a...@openchip.org> wrote in message >> news:drcq39$imr$00$1...@news.t-online.com... >>> >Marco T." <m...@blabla.com> schrieb im Newsbeitrag >>> >news:drcptn$ueq$1...@nnrp.ngi.it... >>>> Hallo, >>>> I would develop a system based on opb multichannel memory sdram >>>> controller. >>>> >>>> I would connect Microblaze to the controller using xcl and not opb bus. >>>> >>>> I would also connect an external microcontroller to sdram: I thought to >>>> create a custom opb master peripheral and connect it to opb bus. >>>> >>>> The opb bus will have a master (the external micro) and a slave (the >>>> sdram). >>>> >>>> Is it reliable? >>>> >>>> When I access memory from the external micro, may I use the address >>>> generated using EDK Platform Studio? >>>> >>>> In this way I should have the memory controller mapped in example at >>>> 0X22000000. >>>> >>>> May I use this address to gain access from microblaze and the external >>>> microcontroller? >>>> >>>> Many Thanks >>>> Marco >>>> >>> whatever you connect to OPB bus can not have access to memory on XCL >>> as cachelink FSL bus is accessible only from MicroBlaze, not from busses >>> connected to MB >>> >>> -- >>> Antti Lukats >>> http://www.xilant.com >>> >> >> As usual, my english is terrible... I'm sorry! I try to be more clear. >> >> Microblaze will access sdram through XCL. Microblaze will NOT be >> connected to opb bus. >> >> An external micro will access sdram through OPB bus. It will be a master, >> the only master of the opb bus. The memory controller will be the only >> slave of opb bus. >> >> Is it reliable? >> >> Can Microblaze write a region of sdram and "simultaneously" external >> micro read another region? >> >> Sorry again! >> >> Marco >> > > almost anything can be made reliable, but what you are suggesting is not > REASONABLE. > > if SDRAM is on XCL then whatever external micro should access the SDRAM > controller > that does arbitration directly - using OPB here is not a good idea. > > Antti > > So, a better approach, could be that external micro accesses sdram through another XCL channel? I dont have found lots of information about developing a XCL master peripheral. What is your suggestion? Thanks Antti, your help is always precious! Marco
Re: Multichannel Opb Memory Controller question - Antti Lukats - 2006-01-27 05:12:00
"Marco T." <m...@blabla.com> schrieb im Newsbeitrag news:drcrch$v1f$1...@nnrp.ngi.it... > > "Antti Lukats" <a...@openchip.org> wrote in message > news:drcqsu$2rq$02$1...@news.t-online.com... >> "Marco T." <m...@blabla.com> schrieb im Newsbeitrag >> news:drcqlq$um5$1...@nnrp.ngi.it... >>> >>> "Antti Lukats" <a...@openchip.org> wrote in message >>> news:drcq39$imr$00$1...@news.t-online.com... >>>> >Marco T." <m...@blabla.com> schrieb im Newsbeitrag >>>> >news:drcptn$ueq$1...@nnrp.ngi.it... >>>>> Hallo, >>>>> I would develop a system based on opb multichannel memory sdram >>>>> controller. >>>>> >>>>> I would connect Microblaze to the controller using xcl and not opb >>>>> bus. >>>>> >>>>> I would also connect an external microcontroller to sdram: I thought >>>>> to create a custom opb master peripheral and connect it to opb bus. >>>>> >>>>> The opb bus will have a master (the external micro) and a slave (the >>>>> sdram). >>>>> >>>>> Is it reliable? >>>>> >>>>> When I access memory from the external micro, may I use the address >>>>> generated using EDK Platform Studio? >>>>> >>>>> In this way I should have the memory controller mapped in example at >>>>> 0X22000000. >>>>> >>>>> May I use this address to gain access from microblaze and the external >>>>> microcontroller? >>>>> >>>>> Many Thanks >>>>> Marco >>>>> >>>> whatever you connect to OPB bus can not have access to memory on XCL >>>> as cachelink FSL bus is accessible only from MicroBlaze, not from >>>> busses >>>> connected to MB >>>> >>>> -- >>>> Antti Lukats >>>> http://www.xilant.com >>>> >>> >>> As usual, my english is terrible... I'm sorry! I try to be more clear. >>> >>> Microblaze will access sdram through XCL. Microblaze will NOT be >>> connected to opb bus. >>> >>> An external micro will access sdram through OPB bus. It will be a >>> master, the only master of the opb bus. The memory controller will be >>> the only slave of opb bus. >>> >>> Is it reliable? >>> >>> Can Microblaze write a region of sdram and "simultaneously" external >>> micro read another region? >>> >>> Sorry again! >>> >>> Marco >>> >> >> almost anything can be made reliable, but what you are suggesting is not >> REASONABLE. >> >> if SDRAM is on XCL then whatever external micro should access the SDRAM >> controller >> that does arbitration directly - using OPB here is not a good idea. >> >> Antti >> >> > > > So, a better approach, could be that external micro accesses sdram through > another XCL channel? > > I dont have found lots of information about developing a XCL master > peripheral. > > What is your suggestion? > > Thanks Antti, your help is always precious! > > Marco > you need sdram controller that has XCL port to microblaze and defined by interface to your external micro. -- Antti Lukats http://www.xilant.com______________________________
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Re: Multichannel Opb Memory Controller question - Marco T. - 2006-01-27 05:54:00
"Antti Lukats" <a...@openchip.org> wrote in message news:drcrn1$tge$03$1...@news.t-online.com... > "Marco T." <m...@blabla.com> schrieb im Newsbeitrag > news:drcrch$v1f$1...@nnrp.ngi.it... >> >> "Antti Lukats" <a...@openchip.org> wrote in message >> news:drcqsu$2rq$02$1...@news.t-online.com... >>> "Marco T." <m...@blabla.com> schrieb im Newsbeitrag >>> news:drcqlq$um5$1...@nnrp.ngi.it... >>>> >>>> "Antti Lukats" <a...@openchip.org> wrote in message >>>> news:drcq39$imr$00$1...@news.t-online.com... >>>>> >Marco T." <m...@blabla.com> schrieb im Newsbeitrag >>>>> >news:drcptn$ueq$1...@nnrp.ngi.it... >>>>>> Hallo, >>>>>> I would develop a system based on opb multichannel memory sdram >>>>>> controller. >>>>>> >>>>>> I would connect Microblaze to the controller using xcl and not opb >>>>>> bus. >>>>>> >>>>>> I would also connect an external microcontroller to sdram: I thought >>>>>> to create a custom opb master peripheral and connect it to opb bus. >>>>>> >>>>>> The opb bus will have a master (the external micro) and a slave (the >>>>>> sdram). >>>>>> >>>>>> Is it reliable? >>>>>> >>>>>> When I access memory from the external micro, may I use the address >>>>>> generated using EDK Platform Studio? >>>>>> >>>>>> In this way I should have the memory controller mapped in example at >>>>>> 0X22000000. >>>>>> >>>>>> May I use this address to gain access from microblaze and the >>>>>> external microcontroller? >>>>>> >>>>>> Many Thanks >>>>>> Marco >>>>>> >>>>> whatever you connect to OPB bus can not have access to memory on XCL >>>>> as cachelink FSL bus is accessible only from MicroBlaze, not from >>>>> busses >>>>> connected to MB >>>>> >>>>> -- >>>>> Antti Lukats >>>>> http://www.xilant.com >>>>> >>>> >>>> As usual, my english is terrible... I'm sorry! I try to be more clear. >>>> >>>> Microblaze will access sdram through XCL. Microblaze will NOT be >>>> connected to opb bus. >>>> >>>> An external micro will access sdram through OPB bus. It will be a >>>> master, the only master of the opb bus. The memory controller will be >>>> the only slave of opb bus. >>>> >>>> Is it reliable? >>>> >>>> Can Microblaze write a region of sdram and "simultaneously" external >>>> micro read another region? >>>> >>>> Sorry again! >>>> >>>> Marco >>>> >>> >>> almost anything can be made reliable, but what you are suggesting is not >>> REASONABLE. >>> >>> if SDRAM is on XCL then whatever external micro should access the SDRAM >>> controller >>> that does arbitration directly - using OPB here is not a good idea. >>> >>> Antti >>> >>> >> >> >> So, a better approach, could be that external micro accesses sdram >> through another XCL channel? >> >> I dont have found lots of information about developing a XCL master >> peripheral. >> >> What is your suggestion? >> >> Thanks Antti, your help is always precious! >> >> Marco >> > you need sdram controller that has XCL port to microblaze and defined by > interface to your external micro. > > > -- > Antti Lukats > http://www.xilant.com > > Xilinx Multi-Channel SDRAM Memory controller has 4 XCL ports. Microblaze uses 2 port. Now I should develop a XCL Master interface and connect it to one of the 2 free ports. But I don't have found any document about it. Only about connecting microblaze to memory. I could insert two microblaze into the project, but in what way may I execute different softwares? The second microblaze should only read and trasmit datas out of fpga.
Re: Multichannel Opb Memory Controller question - Antonio Pasini - 2006-01-27 07:12:00
Xilinx Multi-Channel SDRAM Memory controller has 4 XCL ports. Microblaze > uses 2 port. > Now I should develop a XCL Master interface and connect it to one of the 2 > free ports. Marco, I need to the the same thing. Let's keep in touch one each other! Besides... if your english is a problem... are you Italian ? I am. I'll have a MB connected to OPB, using 2 XCL ports for cache; MCH_SDRAM_OPB, some UARTs, all on OPB. Then I need to develop two XCL "masters" to read/write high speed data from the remaining two XCL channels. Can we help one each other ?______________________________
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Re: Multichannel Opb Memory Controller question - Marco T. - 2006-01-27 11:32:00
"Antonio Pasini" <r...@tin.it> wrote in message news:43da0e43$0$22090$4...@reader1.news.tin.it... > Xilinx Multi-Channel SDRAM Memory controller has 4 XCL ports. Microblaze >> uses 2 port. >> Now I should develop a XCL Master interface and connect it to one of the >> 2 free ports. > > Marco, I need to the the same thing. Let's keep in touch one each other! > Besides... if your english is a problem... are you Italian ? I am. > > I'll have a MB connected to OPB, using 2 XCL ports for cache; > MCH_SDRAM_OPB, some UARTs, all on OPB. > Then I need to develop two XCL "masters" to read/write high speed data > from the remaining two XCL channels. > > Can we help one each other ? > > > > Hello Antonio, I have opened also a webcase about this trouble. They told me to watch mch_opb_ipif core, into cores directory. But it seems to be still not ready for use. Marco
Re: Multichannel Opb Memory Controller question - =?ISO-8859-1?Q?G=F6ran_Bilski?= - 2006-01-27 11:35:00
Antonio Pasini wrote: > Xilinx Multi-Channel SDRAM Memory controller has 4 XCL ports. Microblaze > >>uses 2 port. >>Now I should develop a XCL Master interface and connect it to one of the 2 >>free ports. > > > Marco, I need to the the same thing. Let's keep in touch one each other! > Besides... if your english is a problem... are you Italian ? I am. > > I'll have a MB connected to OPB, using 2 XCL ports for cache; MCH_SDRAM_OPB, > some UARTs, all on OPB. > Then I need to develop two XCL "masters" to read/write high speed data from > the remaining two XCL channels. > > Can we help one each other ? > > > > Unfortunately there is no document solely about the XCL bus. But read the small section in MicroBlaze reference guide on the XCL signals and also look at the timing diagrams in the mch_opb_sdram controller. If it's still unclear email me and I will try to answer your questions. Göran Bilski______________________________
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